New Middleware Technology Quadruples SSD Speed

May 22, 2014
Jyunichi Oshita, Nikkei BP Semiconductor Research
The proposed system
The proposed system
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The proposed control of data writing
The proposed control of data writing
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The results of a simulation of writing speed
The results of a simulation of writing speed
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A Japanese research team developed a technology to drastically improve the writing speed, power efficiency and cycling capability (product life) of a storage device based on NAND flash memory (SSD).

The team is led by Ken Takeuchi, professor at the Department of Electrical, Electronic and Communication Engineering, Faculty of Science and Engineering of Chuo University. The development was announced at 2014 IEEE International Memory Workshop (IMW), an international academic conference on semiconductor memory technologies, which took place from May 18 to 21, 2014, in Taipei. The title of the thesis is "NAND Flash Aware Data Management System for High-Speed SSDs by Garbage Collection Overhead Suppression."

With NAND flash memory, it is not possible to overwrite data on the same memory area, making it necessary to write data on a different area and, then, invalidate the old area. As a result, data is fragmented, increasing invalid area and decreasing storage capacity. Therefore, NAND flash memories carry out "garbage collection," which rearranges fragmented data in a continuous way and erases blocks of invalid area. This process takes 100ms or longer, drastically decreasing the writing speed of SSD.

In September 2013, to address this issue, the research team developed a method to prevent data fragmentation by making improvements to middleware that controls a storage for database applications. It makes (1) the "SE (storage engine)" middleware, which assigns logical addresses when an application software accesses a storage device, and (2) the FTL (flash translation layer) middleware, which converts logical addresses into physical addresses on the side of the SSD controller, work in conjunction. This time, the team developed a more versatile method that can be used for a wider variety of applications.

The new method forms a middleware layer called "LBA (logical block address) scrambler" between the file system (OS) and FTL. The LBA scrambler works in conjunction with the FTL and converts the logical addresses of data being written to reduce the effect of fragmentation.

Specifically, instead of writing data on a new blank page, data is written on a fragmented page located in the block to be erased next. As a result, the ratio of invalid pages in the block to be erased increases, reducing the number of valid pages that need to be copied to another area at the time of garbage collection.

In a simulation, the research team confirmed that the new technology improves the writing speed of SSD by up to 300% and reduces power consumption by up to 60% and the number of write/erase cycles by up to 55%, increasing product life. Because, with the new method, it is not necessary to make any changes to NAND flash memory, and the method is completed within the middleware, it can be applied to existing SSDs as it is.