Intel Plans to Scale Ultra-low Voltage Transistor Beyond 10nm

Dec 19, 2013
Jyunichi Oshita, Nikkei BP Semiconductor Research
Tunnel FETs with double-gate and nanowire structures
Tunnel FETs with double-gate and nanowire structures
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The properties of a tunnel FET having the nanowire structure
The properties of a tunnel FET having the nanowire structure
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Introduction of a resonant tunneling structure
Introduction of a resonant tunneling structure
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The properties with the resonant tunneling structure
The properties with the resonant tunneling structure
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Intel Corp announced its strategies for scaling down its tunnel FET, a transistor that can be driven with a voltage lower than 0.4V, by using its next-generation process technology with an 9nm or smaller gate length.

The announcement was made at International Electron Devices Meeting (IEDM) 2013, which took place from Dec 9 to 11, 2013, in Washington, D.C. (lecture number: 4.3).

With a gate length of about 9nm or longer, by combining a tunnel FET with a nanowire structure, it is possible to use a power supply voltage of less than 0.4V and ensure a higher on-state current than that of a silicon (Si) nanowire transistor, Intel said. Moreover, if a structure that enables to ensure a higher on-state current than a normal tunnel FET by using resonant tunneling effect is introduced, gate length can be reduced to less than 9nm.

This time, Intel tested a tunnel FET having a heterostructure of GaSb and InAs. In a simulation, the company examined how current driving capability changes depending on transistor size with the introduction of a double-gate, nanowire or resonant tunneling structure.

The tunnel FET technology makes the rise of on-state current precipitous, compared with Si-MOSFETs, by using inter-band tunneling effect (a kind of quantum effect) for the electrical conduction of transistor. Because it enables to ensure a high current driving capability with a lower power supply voltage, compared with Si-MOSFETs, it is highly expected to be used as an ultra-low voltage transistor.

In the test, Intel used an Si-MOSFET with a gate length of about 9nm, which will be realized in about 2022, for comparison. If a double-gate or nanowire structure is introduced to a GaSb/InAs tunnel FET, with a gate length of 9nm, both of the structures realize higher current driving capabilities than the Si-MOSFET. And the nanowire structure, which enables to increase the thickness of the body part, is superior to the double-gate structure in terms of manufacturing technologies.

A GaSb/InAs tunnel FET having a 3nm-diameter nanowire structure ensures an about 10-20 times higher on-state current with a power supply voltage less than 0.4V, compared with a Si nanowire transistor. Its S-value (a parameter that indicates the rising speed of on-state current) is 47mV/decade, which is better than the Si-MOSFET's theoretical limit (about 60mV/decade).

If a resonant tunneling structure having a quantum well on the hetero interface is formed by replacing the source and drain materials of the tunnel FET, S-value can be improved to 25mV/decade, Intel said. As a result, it will become possible to realize an about 100 time higher on-state current with a very low power supply voltage (0.27V), compared with the Si-MOSFET.

In general, the S-value of a tunnel FET tends to deteriorate as the gate length becomes shorter. On the other hand, Intel concluded that it is possible to shorten the gate length of its tunnel FET to less than 9nm by using a resonant tunneling structure.