TSMC Explains 16nm Process Technology; FinFET Introduced
TSMC (Taiwan Semiconductor Manufacturing Co Ltd) announced a 16nm process technology that it will start to use for small-quantity production by the end of 2013.
The announcement was made at International Electron Devices Meeting (IEDM) 2013, which took place from Dec 9 to 11, 2013, in Washington, D.C. (lecture number: 9.1).
The technology is designed for the SoCs (systems on a chip) of mobile and computing devices. For the technology, the company has employed a three-dimensional transistor (FinFET) for the first time. Compared with its 28nm process technology (high-k gate dielectric film/metal gate), the density of transistors increased by 100%, enabling to increase their operation speed by 35% or decreasing their power consumption by 55%.
TSMC is currently using its 20nm process technology (20SOC) for small-quantity production and will start using the subsequent 16nm process technology for small-quantity production soon. With the 16nm process technology, the company has already prototyped SRAM, a ring oscillator and test chip equipped with ARM Ltd's "Cortex-A57" processor core. In the lecture, it explained the details of the process technology, transistor characteristics, prototyped SRAM, etc.
The 16nm process technology is based on the BEOL (back end of line) metal interconnection technology used for the 20nm process but uses FinFETs in place of planar transistors. The FinFETs are combined with a high-k gate dielectric film/metal gate using the gate-last (replacement gate) method that is similar to the method used for the 28nm process technology.
For the 16nm process technology, TSMC employed seven-layer Cu-low-k interconnection. The half pitch of the first metal interconnection is 32nm. The fin pitch is 48nm. The company uses 30, 34, and 50nm gate lengths. Double-patterning and pitch-splitting techniques are used for the patterning of the first metal interconnection and the formation of fins, respectively.
In regard to the on-state current of the prototyped low leakage transistor (gate length: 34nm), it is 520μA/μm for the nMOS and 525μA/μm for the pMOS with a power supply voltage of 0.75V and an off leakage current of 30pA/μm. As for its short-channel characteristics, its DIBL (drain induced barrier lowering) is less than 30mV/V, which is preferable.
In addition, TSMC reduced characteristic variation for the transistor, reducing AVt, an indicator of variation, by 36% for the nMOS and 24% for the pMOS, compared with the 28nm process.
Furthermore, TSMC prototyped a 128-Mbit SRAM chip and confirmed that it can be produced with a high yield rate and fully functions. With a high-density SRAM that uses only one fin for each transistor, the company achieved an SNM (static noise margin) of 120mV with a cell area of 0.7μm2 and power supply voltage of 0.6V.
For the SRAM, TSMC reduced minimum driving voltage by 220mV, compared with the case where planar transistors are used. The picture of the prototyped chip was not published in the thesis but showed with a slide projector.