Samsung Discloses Details of 'V-NAND' 3D NAND Flash
Samsung Electronics Co Ltd delivered a keynote speech on the "Vertical NAND (V-NAND)" 3D NAND flash memory at Flash Memory Summit (FMS) 2013.
The company announced Aug 6, 2013, that it had started volume production of the memory (See related article). FMS 2013 is an international conference/exhibition on flash memory technologies. It took place from Aug 13 to 15, 2013, in Santa Clara, Calif, the US.
This time, Samsung explained technologies that realized the V-NAND and its basic properties and announced that it has started to ship samples of enterprise SSDs equipped with the memory. The title of the speech was "Ushering in the 3D Memory Era with V-NAND."
E.S. Jung, executive vice president, general manager, Semiconductor R&D Center, Samsung Electronics, who took the podium, said that planar floating-gate NAND flash memories made using 1Xnm process technology are reaching their limits mainly because of two reasons.
One is an increase in the interference among adjacent memory cells (physical limit). The other is an increase in lithography cost (economic limit).
Samsung considers that 3D NAND flash memory, which three-dimensionally stacks memory cells to increase bit density, can solve those problems. For the V-NAND, the company employed a charge-trap film, which stores electrons in a SiN film, in place of a floating gate (polycrystalline silicon (Si)) in the planar structure. By stacking 24 layers of memory cells made using 30-40nm process technologies, density was doubled, compared with planar NAND made using 20nm process technology, the company said.
By using 30-40nm process technologies instead of 20nm-or-so process technology, it becomes possible to solve the problem of the interference among cells and the problem of lithography cost at the same time, it said.
The largest challenge in realizing the V-NAND lies in the process of boring a hole that penetrates the multi-layer film. This process is necessary for forming multi-layer memory cells at one time. The number of such holes is 2.5 billion (50,000 x 50,000). The aspect ratio is about 40.
The performance of the V-NAND is superior to that of planar NAND, Jung said. The writing speed, cycling capability and power consumption of the 2-bit-per-cell (MLC) 128-Gbit V-NAND, which Samsung is currently mass-producing, are respectively two times, 10 times (100,000 times) and half those of planar NAND made using 20nm process technology.
The writing speed became faster because data can be written with one-time writing operation per word line (one time programming) due to the small interference among cells between word lines. The higher cycling capability was realized because the number of electrons that each memory cell can hold increased by about 200% to about 1,000. The power consumption was lowered because the writing current was reduced to 14mA, which is half that of planar NAND, by improving circuit design, etc.
In general, charge-trap cells are slow in deleting data. But Jung did not clearly comment on this issue, saying, "It depends on the circuit design of each application."
In regard to the volume production of the V-NAND, he said, "It is smoothly starting up with a reasonable yield rate and a low cost." He also said that it will become possible to realize a memory capacity of 1 Tbit or higher per chip by increasing the number of stacked memory cell layers.
According to its roadmap, Samsung will realize a 1-Tbit chip in 2017. Also, the company said it is possible to realize TLC (3-bit-per-cell) in the future.