Toshiba Develops Fundamental Technology for Gbit-class STT-MRAM
Toshiba Corp developed a perpendicular magnetization-type magnetic tunnel junction (MTJ) device that has excellent properties and is a basic element to realize a gigabit-class spin torque transfer MRAM (STT-MRAM).
Its rewriting current density, which determines data writing electricity, is 5 x 105Acm-2, which is 1/6 that of the company's existing products. And its magnetic resistance (MR), which determines data reading margin, is 200%, which was drastically improved from the 15% of the existing products.
"We will shift from the development of elemental technologies to the development of products using the latest research results," Toshiba said.
Toshiba plans to commercialize a gigabit-class STT-MRAM within three or four years, expecting that it will be used as non-volatile memory for random access data, which are frequently rewritten and read out.
Specifically, it is expected to be used as the cache memories of HDDs and SSDs and to replace part of the DRAMs and low- and medium-speed SRAMs in smartphones, notebook computers and other mobile devices. By replacing the main memories or cache memories of devices with STT-MRAMs, it becomes possible to realize a "normally off" operation, Toshiba said.
It has been difficult to realize a low rewriting current density and a high MR ratio at the same time with traditional perpendicular magnetization-type MTJ devices because there is a trade-off between rewriting current density and MR ratio. This time, Toshiba solved this problem by using materials that are based on cobalt (Co) and iron (Fe), which are prone to magnetization reversal, for the recording (free) layer, which is one of the two ferromagnetic electrodes constituting an MTJ device.
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As a result, the company reduced the rewriting current of a 50nm-diameter MTJ device to 9μA. Also, it has already confirmed that an MTJ device with a diameter as small as 30nm functions properly.
According to Toshiba, to realize a gigabit-class STT-MRAM, it is necessary to have a rewriting current density of 106Acm-2 or lower and an MR ratio of 200% or higher at the same time. This time, the company realized this goal.
When the latest results are compared with the prediction that ITRS (International Technology Roadmap for Semiconductors) made about STT-MRAM, the specifications that Toshiba achieved this time are superior to those that ITRS predicted for the year 2024, the company said. According to the prediction made by ITRS, the design rule (minimum process size) will be 16nm and the cell area will be 8F2 (F: design rule) in 2024.
This means that the process size and cell area of the new MTJ device developed by Toshiba can be further reduced.
"(In the phase of volume production), we aim at a process size one generation older than that of DRAM and a cell area of 6F2," the company said. "In theory, its production cost can be equivalent to that of DRAM."
Toshiba announced the results of the development of a 64-Mbit STT-MRAM using a perpendicular magnetization-type MTJ device at ISSCC 2010, which took place in February 2010 in San Francisco, the US. Currently, the company seems to be evaluating a large-capacity array (more than several hundred megabits). As one of the problems that have to be solved to commercialize the memory, the company said that it is necessary to reduce the variation in operation.