Toshiba Develops Fundamental Technology for Gbit-class STT-MRAM (page 2)

Jul 6, 2011
Jyunichi Oshita, Nikkei Electronics

As a result, the company reduced the rewriting current of a 50nm-diameter MTJ device to 9μA. Also, it has already confirmed that an MTJ device with a diameter as small as 30nm functions properly.

According to Toshiba, to realize a gigabit-class STT-MRAM, it is necessary to have a rewriting current density of 106Acm-2 or lower and an MR ratio of 200% or higher at the same time. This time, the company realized this goal.

When the latest results are compared with the prediction that ITRS (International Technology Roadmap for Semiconductors) made about STT-MRAM, the specifications that Toshiba achieved this time are superior to those that ITRS predicted for the year 2024, the company said. According to the prediction made by ITRS, the design rule (minimum process size) will be 16nm and the cell area will be 8F2 (F: design rule) in 2024.

This means that the process size and cell area of the new MTJ device developed by Toshiba can be further reduced.

"(In the phase of volume production), we aim at a process size one generation older than that of DRAM and a cell area of 6F2," the company said. "In theory, its production cost can be equivalent to that of DRAM."

Toshiba announced the results of the development of a 64-Mbit STT-MRAM using a perpendicular magnetization-type MTJ device at ISSCC 2010, which took place in February 2010 in San Francisco, the US. Currently, the company seems to be evaluating a large-capacity array (more than several hundred megabits). As one of the problems that have to be solved to commercialize the memory, the company said that it is necessary to reduce the variation in operation.