[SID] Sony Announces OLED Panel With Self-aligned Top-gate Oxide TFT
Sony Corp developed an OLED panel whose image quality was improved by reducing the unevenness of brightness and announced it at the 49th SID International Symposium, Seminar & Exhibition (SID 2011).
The company showcased a prototype of the panel in the author's interview that followed the announcement. Many researchers gathered around the panel and gazed at images displayed on it while it was being demonstrated.
As one of the causes of the brightness unevenness of OLED panels, there is a problem of parasitic capacitance that is generated between the gate electrode and source/drain electrode of TFT (thin-film transistor). The value of the parasitic capacitance fluctuates on some parts of the screen, generating brightness unevenness.
This brightness unevenness is apparent especially on the side of low gradation. If the parasitic capacitance of TFT can be lowered enough, the problem of brightness unevenness will be solved.
This time, Sony reviewed the structure of TFT. Specifically, it employed a self-aligned top-gate structure instead of the bottom-gate structure it has been using. With a self-aligned top-gate structure, it becomes possible to keep a long distance between a gate electrode and a source/drain electrode, enabling to reduce parasitic capacitance enough.
To introduce the self-aligned top-gate structure, Sony developed a new manufacturing process technology. It consists mainly of four processes: (1) patterning with a dry-etching method after forming oxide semiconductor IGZO (indium gallium zinc oxide), gate insulating film and gate electrodes on a glass substrate, (2) forming an aluminum (Al) thin film on it with a sputtering method, (3) forming an aluminum oxide (Al2O3) protective layer by oxidizing Al in an oxygen annealing process and a low-resistance layer by dispersing Al on the surface of the oxide semiconductor and (4) forming source/drain electrodes by opening via holes after forming an organic layer in a coating process.
The Al2O3 protective layer and the low-resistance layer on the surface of the oxide semiconductor formed in the third process realize not only a stability to annealing treatment, which is necessary to improve the performance of TFT, but also a high reliability. Also, the number of mask processes required for the manufacturing process is only four, thus reducing costs.
Furthermore, with a self-aligned top-gate structure, the channel length of TFT becomes short, making it easy to deal with large screen size and high resolution of OLED panels as well as increase in drive frequency.
The OLED panel that Sony prototyped this time has a screen size of 9.9 inches and a pixel count of 960 x 540. Its brightness is 200cd/m2 with an all-white signal and 600cd/m2 or higher at its peak. Also, the panel's contrast ratio is 1,000,000:1 or higher, and its color gamut is 96% on NTSC standards.
Correction Notice: Because of a reporting error, we incorrectly stated "by dispersing enzyme on the surface of the oxide semiconductor" in the 6th paragraph when it should have been "by dispersing Al on the surface of the oxide semiconductor."