Elpida, Sharp et al Team for ReRAM

Oct 13, 2010
Motoyuki Oishi, Nikkei Electronics
The architecture of an SSD using nonvolatile memory (such as ReRAM) as cache memory
The architecture of an SSD using nonvolatile memory (such as ReRAM) as cache memory
[Click to enlarge image]

A large joint development project on a next-generation memory chip was launched in Japan.

Elpida Memory Inc, Sharp Corp, the University of Tokyo and Japan's National Institute of Advanced Industrial Science and Technology (AIST) started to co-develop a gigabit-class resistive random access memory (ReRAM) chip. They will combine Sharp's material technologies such as related to resistance change devices and Elpida's volume production technologies for memory chips.

The next-generation memory chip is expected to be used as, for example, cache memory that is positioned between DRAM and NAND flash memory and is for various mobile devices and stationary devices.

The data transmission speed of DRAM, which is used as work memory of electronic devices, is recently increasing because of the introduction of the DDR3 interface, etc. And the speed is expected to continue to increase due to the future introduction of the DDR4 interface. On the other hand, the speed performance (such as writing speed) of NAND flash memory, which is increasingly being used as a storage medium, is decreasing as its capacity is increasing due to, for example, multi-valuing.

"Because the difference in performance between DRAM and NAND flash memory is continuously growing, it is necessary to develop a new nonvolatile memory device that can fill the gap," said Takao Adachi, Elpida's CTO.

To meet that goal, Elpida, Sharp, the University of Tokyo and AIST chose ReRAM, whose writing speed is much faster than that of NAND flash memory. And they aim to realize ReRAM with a capacity at least as high as that of DRAM.

Along with the development of the gigabit-class ReRAM, they began to quantitatively estimate how much the performances and the power consumptions of electronic devices can be improved by using the ReRAM.

A research group led by Ken Takeuchi, associate professor at the Department of Electrical Engineering and Information Systems, Graduate School of Engineering of the University of Tokyo, announced the results of the estimation at SSDM (Solid State Devices and Materials) 2010, an international conference on semiconductor devices and materials that took place from Sept 22 to 24, 2010, in Tokyo. The group is developing ReRAM in collaboration with Elpida and Sharp.

Specifically, when ReRAM is used as the cache memory of an SSD (solid state drive), it is possible to reduce power consumption by 97% and to increase tolerable bit error rate, which is an indicator of operation reliability, by 260%.