STT-MRAM Cuts Cache Memory Power Consumption by 60%

Jun 11, 2014
Jyunichi Oshita, Nikkei BP Semiconductor Research

Toshiba Corp developed an STT-MRAM (spin transfer torque magnetoresistive random access memory) that can realize the industry's highest performance as a cache memory for microprocessors.

By replacing an SRAM used for cache with the new STT-MRAM, it is possible to reduce the power consumption of the cache memory, which accounts for most of the power consumed by a processor, by about 60%, Toshiba said. The details of the new technology will be announced at the 2014 Symposia on VLSI Technology and Circuits, which runs from June 9 to 13, 2014, in Honolulu, the US, in a lecture titled "Highly Reliable and Low-Power Nonvolatile Cache Memory with Advanced Perpendicular STT-MRAM for High-Performance CPU" (lecture number: C12-1).

Non-volatile cache

Toshiba has long been engaged in the development of STT-MRAM to be used as a cache memory of a processor (See related article). The power consumptions of the latest processors are largely accounted for by the power consumption of SRAM used as a cache memory. For example, the leak power of the L2 cache accounts for about 80% of the power consumption of a processor.

Therefore, if SRAMs used as L2-L4 cache memories are replaced with non-volatile STT-MRAMs to reduce leak power, the power consumption of a processor can be drastically reduced.

However, there have been two challenges in replacing SRAM cache with STT-MRAM. First, there is a trade-off between operation speed and leak power. An SRAM (6T-2MTJ)-type circuit structure realizes a fast operation speed but leaves the path of leak current (leak path). On the other hand, a DRAM (1T-1MTJ)-type circuit structure eliminates the leak path but slows operation speed.

Second, if a Mbit-class array, which is required for cache, is formed, the number of errors will increase due to process variation.

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