Samsung Electronics Co Ltd made an announcement about its "Vertical NAND (V-NAND)" 3D NAND flash memory at International Solid-State Circuits Conference (ISSCC) 2014 (lecture number: 19.5).
The conference took place from Feb 9 to 13, 2014, in San Francisco, the US. The V-NAND is an MLC (multi-level cell) product using 24 memory cell layers and has a capacity of 128 Gbits per chip.
In August 2013, Samsung announced that it had started volume production of the V-NAND (See related article). Also, the company announced the details of the memory at Flash Memory Summit 2013, which took place in the US during the same period (See related article 2).
The area of the V-NAND chip is 133mm2, which is smaller than the area of the new 16nm 128Gbit NAND flash memory chip that Micron Technology Inc announced at ISSCC 2014 (173.3mm2). The bit density of the V-NAND is 0.96 Gbits/mm2, which Samsung claims is the highest in the industry.
However, the current manufacturing cost of the V-NAND is considered to be higher than that of the latest planar NAND. It is because 3D NAND requires, for example, a process of opening high-aspect-ratio memory holes in its stacked films, requiring new capital investments.
The 24-layer V-NAND that Samsung announced this time is the first-generation product. And many consider that only the second- or third-generation product with an increased number of memory cell layers will be able to compete with planar NAND in cost. The company plans to release 1-Tbit V-NAND in or after 2017.
For the first-generation V-NAND, Samsung emphasized its high performance and reliability. It seems that the company targets the latest technology at high-performance applications such as enterprise SSDs and will see how users will respond.
If the technology is used for an enterprise SSD, it will realize a write/erase endurance of 35,000 cycles with a write throughput of 36 Mbytes per second, Samsung said. For embedded applications, it will realize a write/erase endurance of 3,000 cycles with a write throughput of 50 Mbytes per second. However, some of the audience doubted that it is really possible to realize a high reliability with the 3D NAND having a totally new structure.
On the other hand, it is unclear how much planar NAND can be further miniaturized. The 16nm 128Gbit NAND flash memory that Micron Technology announced has a half-pitch of 16nm in the direction of word lines. But its half-pitch is 20.5nm in the direction of bit lines and has not been changed this time. So, it can be further miniaturized.
Furthermore, in consideration of the recent accelerating development of error correction technologies, it might be possible to deal with the increase in bit-error ratio caused by microfabrication by making improvements to system technologies. If that is the case, it might extend the limitation of planar NAND. The battle between 2D NAND and 3D NAND has just begun. And it is worth paying attention to how the market will respond.