Micron, Sony Develop 16Gb High-speed ReRAM

Feb 16, 2014
Masahide Kimura, Nikkei BP Semiconductor Research
A 16-Gbit ReRAM made using 27nm process technology
A 16-Gbit ReRAM made using 27nm process technology
[ If it clicks, the expanded picture will open ]
It is targeted at a storage-class memory that fills the gap between DRAM and NAND.
It is targeted at a storage-class memory that fills the gap between DRAM and NAND.
[ If it clicks, the expanded picture will open ]
This is the first time that a high-speed, high-capacity ReRAM has been reported.
This is the first time that a high-speed, high-capacity ReRAM has been reported.
[ If it clicks, the expanded picture will open ]
The structure of the resistance change element
The structure of the resistance change element
[ If it clicks, the expanded picture will open ]

A research team consisting of researchers from Micron Technology Inc and Sony Corp developed a 16-Gbit ReRAM (resistive random access memory) by using 27nm process technology.

The development was announced at International Solid-State Circuits Conference (ISSCC) 2014, which took place from Feb 9 to 13, 2014, in San Francisco, the US (lecture number: 19.7). The team aims to apply the ReRAM to a storage-class memory (SCM) that fills the speed gap between DRAM and NAND flash memory.

At ISSCC 2013, a group consisting of researchers from SanDisk Corp and Toshiba Corp announced a 32-Gbit bilayer cross-point ReRAM (See related article). But it was designed to replace NAND flash. And its access latencies for reading and writing are as slow as 40μs and 230μs, respectively.

Though ReRAMs capable of being accessed at high speeds have already been developed, no gigabit-class memory has been reported. On the other hand, the 16-Gbit ReRAM has both "a capacity higher than that of DRAM" and "speed higher than that of NAND," which are required for SCMs.

For the ReRAM, the research team employed a 1Gbps DDR interface and eight bank memory architecture, which is similar to DRAM. Its speed was improved by parallel operation and pipeline data path. Its data transmission speed is 1 Gbyte per second for reading and 200 Mbytes per second for writing. And its latencies for reading and writing are 2μs and 10μs, respectively.

For its resistance change element, the team used a bilayer structure consisting of a CuTe film and insulating film, and resistance value is changed by the movement of Cu ions. It is called CBRAM (conductive-bridge memory). The memory cell consists of a selection transistor and resistance change element (1T1R).

The ReRAM is manufactured by using 27nm triple-layer Cu interconnection process technology. Its cell area is 6F2 (4,374nm2), which is similar to DRAM. Its chip area is 168mm2.

The latest technology is targeted at SCMs. But it is unclear whether the technology is used for servers at data centers, smartphones or tablet computers. Sony said that it is considering a wide variety of applications.

The new ReRAM needs to go through a process called "forming," which applies a voltage to the resistance change element to make it operable. But some of the audience pointed out that the process might increase costs.