SK Hynix Reveals 16nm NAND Flash Technology for Volume Production

Dec 22, 2013
Jyunichi Oshita, Nikkei BP Semiconductor Research
A cross-section of the memory cell developed by SK Hynix
A cross-section of the memory cell developed by SK Hynix
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The characteristics of the interference between bit lines
The characteristics of the interference between bit lines
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Endurance characteristics
Endurance characteristics
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Threshold voltage distribution
Threshold voltage distribution
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SK Hynix Inc announced its "Middle-1X (M1X)"-nm-generation multiple-level NAND flash memory technology, disclosing the details of its 16nm process technology, which it started to use for full-scale production in November 2013.

The announcement was made at International Electron Devices Meeting (IEDM) 2013, which took place from Dec 9 to 11, 2013, in Washington, D.C. (lecture number: 3.6).

SK Hynix introduced air gaps not only in the direction of bit lines (between word lines) but in the direction of word lines (between bit lines) and employed a structure that applies p-type doping to control and floating gates with a high density. As a result, the company ensured a high productivity by reducing interference between memory cells, etc.

SK Hynix announced the generic technology for the M1Xnm process at IEDM 2011 (See related article). For the generic technology, the company increased the space for control gate by reducing the width of floating gate in the direction of word lines. As a result, holes were formed on the control gate, making the gate depleted and preventing the interference between bit lines from increasing.

In the direction of bit lines, the volume of air gap was increased to reduce the electric field applied to the control gate and the adjacent floating gate at the time of writing data, preventing charge leakage from the floating gate. This time, the company added two improvements while using those techniques.

First, it introduced air gaps in the direction of word lines to reduce the interference between bit lines. As a result, the interference was reduced to about 1/3 that of the previous M1Xnm process technology and 1/2 that of the 2Ynm process technology.

The larger the volume of air gap, the less the interference between bit lines becomes. However, the tunnel insulator becomes more likely to be damaged. In consideration of this, SK Hynix optimized the volume of the air gap.

Second, SK Hynix newly employed a structure that applies p-type doping to control and floating gates, which were doped with n-type impurities for its 2Ynm process technology, with a high density. This change prevents the fluctuation of threshold voltage, which is caused by the voltage applied to adjacent word lines at the time of reading data.

High-density p-type doping prevents the depletion of gates, making it easy to reduce the influence of adjacent word lines. Through this improvement, the company achieved endurance and retention characteristics equivalent to those of the 2Ynm process technology.