HOME

Computing Capability, Data Storage Realized Only With STT-MRAM

2013/12/12 11:43
Masahide Kimura, Nikkei BP Semiconductor Research
Print Page

Toshiba Corp announced a new computing architecture that carries out operations and stores data only with STT-MRAM at International Electron Devices Meeting (IEDM) 2013, which took place from Dec 9 to 11, 2013, in Washington, D.C. (lecture number: 25.4).

The title of the lecture was "Variable Nonvolatile Memory Arrays for Adaptive Computing Systems."

Currently, in many computing architectures, a CPU that carries out operations and memory that stores data are separated. And the memory is stratified, consisting of a register file, primary cache and secondary cache. Recently, however, data transmission between a CPU and memory is becoming a bottleneck to improving system performance and power consumption.

In view of this situation, Toshiba proposed the computing architecture, in which one memory chip not only has computing capability but supports register file, primary cache and secondary cache. As a memory for the architecture, the company plans to use a perpendicular STT-MRAM that it has been developing.

To eliminate the bottleneck in data transmission between a CPU and memory, there is a method that "lifts up" memory from the memory hierarchy to the inside of the CPU and disperses it in the CPU. And Toshiba was considering this method in about 2004. However, the method eventually requires a large amount of memory outside of the CPU, making it difficult to improve performance. As a result, the company gave up on it and started to look for a different method.

The new method only requires memory. Specifically, the results of operations (answers) that correspond to combinations of certain inputs are prepared in advance in the form of a table and stored in the memory. In response to an input, an answer is read out of the memory. This is equivalent to an operation carried out by a CPU.

(Continue to the next page)