Computing Capability, Data Storage Realized Only With STT-MRAM (page 2)

Dec 12, 2013
Masahide Kimura, Nikkei BP Semiconductor Research

With the new method, it becomes possible to have a result equivalent to that attained through complicated calculations just by reading out an answer once. Therefore, it drastically improves processing speed and power consumption. In a simulation, Toshiba found that a division process requires 50 processing cycles with a normal CPU but the same division process requires only 16 cycles with the new method.

For a calculation called "Armstrong," which looks for combinations of a, b and c that satisfy the equation 100 x a + 10 x b + c = a3 + b3 + c3, 50 cycles are normally required. But the new method enables to reduce it to 20 cycles. Also, 408 cycles are normally required to solve a quadratic equation, but it can be reduced to 44 cycles.

Of course, the results of operations have to be calculated in advance with an external computer. This is basically the same as the fact that it is necessary for existing computers to compile programs in advance, Toshiba said. Also, because the table in the memory is rewritten depending on the kind of operation, a variety of tables containing the results of operations need to be stored in an external memory.

In principle, it is possible to carry out operations by using SRAM. But its standby power consumption is high. That is why Toshiba ran the simulation for STT-MRAM, which features high speed and non-volatility.

Toshiba announced an MTJ technology aimed at replacing SRAM at IEDM 2012 (See related article). In addition, it announced a high-speed 1-Mbit array having the "two-transistor/two-MTJ (2T-2MTJ)" structure at the 2013 VLSI Symposia. This time, the company ran the simulation based on the values measured with the 1-Mbit array having the 2T-2MTJ structure.