Toshiba Announces Strategies for Its Semiconductor/storage Business

Sep 14, 2013
Jyunichi Oshita, Nikkei BP Semiconductor Research
An image of Fab 5 at Toshiba's Yokkaichi Operations
An image of Fab 5 at Toshiba's Yokkaichi Operations
[Click to enlarge image]

Toshiba Corp had a press meeting to explain about the business of its Semiconductor & Storage Products Company Sept 11, 2013, in Tokyo.

Yasuo Naruke, president of the Semiconductor & Storage Products Company, took the podium.

Compared with fiscal 2008, when Toshiba's semiconductor business recorded a massive deficit, "the memory business came back, but the discrete semiconductor and system chip businesses are halfway to resurgence," Naruke said.

For the future, Toshiba plans to put all the energy into increasing sales of its discrete semiconductors and system chips, whose sales growth has been sluggish, while keeping the advantage of its money-making NAND flash memories. The company predicts that the annual growth rate of the semiconductor market during the period from fiscal 2012 to 2015 will be 3.6% on average. And it aims to increase its semiconductor sales at an average annual rate of 6.8%.

Broadly speaking, the Semiconductor & Storage Products Company deals with "memory," "storage," "discrete" and "system chip." Recently, the company divided the system chip business into "mixed signal chip" and "logic chip." In addition, it transferred the CMOS image sensor business, which had been dealt with by its system chip division, to its memory division.

Memory
The main product of the memory division is NAND flash memory.

"We will take the lead in the development of 3D memories, too, by exceeding scaling limits and will definitely keep the superiority," Naruke said.

Toshiba intends to reduce bit cost by increasing the ratio of 3-bit-per-cell (TLC) memories and employ 1Znm process technology, which follows 1Ynm process technology (the second (current) generation of 19nm process technology). Then, the company will switch to the "BiCS (Bit Cost Scalable)" 3D memory, which three-dimensionally stacks multiple layers of memory cells, to keep the lowered cost, it said.

Among them, Toshiba will start to ship 1Znm products in fiscal 2014 and samples of the first-generation BiCS memory at the end of fiscal 2013. After spreading the samples in the market in fiscal 2014, the company plans to start volume production in fiscal 2015. The number of memory cell layers of the BiCS is scheduled to be 30 or more.

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