TSMC Lectures on 112Mb SRAM With World's Smallest Cell Area

Feb 26, 2013
Masahide Kimura, Nikkei Electronics
The 112-Mbit SRAM manufactured by using 20nm planar-type high-k/metal gate technology
The 112-Mbit SRAM manufactured by using 20nm planar-type high-k/metal gate technology
[Click to enlarge image]
TSMC used a shmoo plot to show that the SRAM functions.
TSMC used a shmoo plot to show that the SRAM functions.
[Click to enlarge image]
The shift from 28nm to 20nm reduced the cell area of SRAM by about 40%.
The shift from 28nm to 20nm reduced the cell area of SRAM by about 40%.
[Click to enlarge image]
The company employed two circuit technologies: "Partial Suppressed Word-Line" (PSWL), which assists reading, and "Bit-Line Length Tracked Negative Bit-Line (BTNBL), which assists writing.
The company employed two circuit technologies: "Partial Suppressed Word-Line" (PSWL), which assists reading, and "Bit-Line Length Tracked Negative Bit-Line (BTNBL), which assists writing.
[Click to enlarge image]
The PSWL and BTNBL increased the chip area of SRAM by 1.2% and 3.7%, respectively.
The PSWL and BTNBL increased the chip area of SRAM by 1.2% and 3.7%, respectively.
[Click to enlarge image]

Taiwan Semiconductor Manufacturing Co Ltd (TSMC) delivered a lecture on a 112-Mbit SRAM manufactured by using 20nm planar-type high-k/metal gate technology at ISSCC 2013 (lecture number: 18.1).

The cell area of the SRAM is 0.081μm2, which is the smallest in the world at this point.

At ISSCC 2012, Intel Corp announced an SRAM that was manufactured by using 22nm FinFET (tri-gate) technology and had a cell area of 0.092μm2.

Of the components of logic chip, SRAM is the most difficult to scale, TSMC said. This time, the company emphasized that the "20SOC," a 20nm logic chip process, has been successful by showing that all the bits of the SRAM perfectly function. The company plans to begin trial production with its 20nm logic chip process during the period from January to March 2013.

Because of the shift from 28nm to 20nm, the cell area of SRAM was reduced by 40%, TSMC said. Also, with circuit technologies that assist reading and writing data (read-write-assist: RWA), the company reduced power supply voltage from 1V (28nm) to 0.95V (20nm).

Specifically, this was realized by using two circuit technologies: "Partial Suppressed Word-Line" (PSWL), which assists reading, and "Bit-Line Length Tracked Negative Bit-Line (BTNBL), which assists writing. The PSWL and BTNBL increased the chip area of SRAM by 1.2% and 3.7%, respectively.