SanDisk, Toshiba Announce 32Gb Bilayer Cross-point ReRAM

Feb 22, 2013
Masahide Kimura, Nikkei Electronics
The 32-Gbit ReRAM chip
The 32-Gbit ReRAM chip
[Click to enlarge image]
It has a 500 times higher capacity than a memory announced at ISSCC 2010.
It has a 500 times higher capacity than a memory announced at ISSCC 2010.
[Click to enlarge image]
Page resisters (PRs) and sense amplifiers (SAs) are arranged under the memory array.
Page resisters (PRs) and sense amplifiers (SAs) are arranged under the memory array.
[Click to enlarge image]

SanDisk Corp and Toshiba Corp co-developed a 32-Gbit bilayer cross-point ReRAM (resistive random access memory) and announced it at ISSCC 2013 (lecture number: 12.1).

Before the development, the 64-Mbit ReRAM that Unity Semiconductor Corp, which is currently owned by Rambus Inc, announced at ISSCC 2010 was the highest-capacity ReRAM developed for replacing NAND flash memory. And the new chip has a 500 times higher memory capacity

The new chip is manufactured using 24nm process technology. It has an effective cell area of 130.7mm2 and a page size of 2 Kbytes. With an interface compatible with NAND flash memory, its latencies for reading and writing are 40μs and 230μs, respectively.

A metal oxide-based resistive device and a cross-point-type architecture having selective devices (diodes) were employed for the area where bit lines and word lines cross. And memory cells can be formed in the circuit layer of a chip.

This time, component density was improved by forming a two-layer memory array on circuits such as page resister and sense amplifier. Such an architecture is similar to a technology developed by Matrix Semiconductor Inc, which was purchased by SanDisk.

However, many engineers who attended the announcement said that it would take time to commercialize the ReRAM. The speaker who announced the memory did not disclose the yield ratio or reliability of the memory, saying that the memory is in its early stage.

For improving the component density of the chip, it is theoretically possible to employ multiple-level cell (MLC) technologies and stack more than two layers of memory arrays, the speaker said.