Toshiba's STT-MRAM Expected to Cut Smartphone Power Consumption
Toshiba Corp developed an STT-MRAM (spin transfer torque magnetic random access memory) base technology for the cache memories of microprocessors used in smartphones, tablet computers, etc.
The technology enables to reduce the power consumptions of the microprocessors in operation to about 1/30 that with currently-used STT-MRAM technologies. With the new technology, it becomes possible to make the most of so-called normally-off operation, which uses non-volatile cache memory and turns off power supply when a device is not in operation.
Currently, the power consumptions of processors in smartphones and tablet computers are increasing partly because the capacities of their cache memories are increasing by about 100% every year. And cache memory accounts for 20-40% of a processor's area, 70% of the transistors and about 50% of the power consumption.
Thus far, SRAM, which is a volatile memory, has been used as cache memory. But ideas of replacing it with a non-volatile memory such as STT-MRAM have been proposed at various events.
However, when a traditional STT-MRAM is used for cache memory or other applications that frequently access memory, it increases power consumption because its operation speed is slow and it consumes a large amount of power when in operation, Toshiba said.
According to the company's estimate, when a traditional STT-MRAM is in operation, its energy (power consumption x operation time) is at least about 1,500pJ, which is 10 times higher than the energy of an SRAM in operation (about 150pJ) including leakage current. So, it does not contribute to lowering power consumption.
To lower power consumption, it is necessary to increase the operation speed of STT-MRAM and lower the power consumed by the memory in operation. Therefore, Toshiba made improvements to the perpendicular magnetic memory element that it developed in 2007 for the first time in the industry. As a result, the power consumption of the memory element in operation was reduced by 90%.
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Though the company did not disclose the details, it said that the improvements were made to the material of the perpendicular magnetic memory element with a width of 30nm and its multilayer structure.
When the energy of the STT-MRAM using the new memory element in operation was calculated in a simulation, it was 46pJ. It is about 1/30 that of a traditional STT-MRAM and 1/3 (or less) that of SRAM, Toshiba said.
Furthermore, Toshiba made improvements to circuits. While its six-transistor SRAM and traditional STT-MRAM cache have a path for leakage current, the company developed a memory circuit that does not have a path for leakage current this time. The memory circuit has a three-transistor/one-MTJ structure and does not cause much leakage current in theory like DRAM, the company said.
As a result, it becomes possible to reduce the power consumption of cache memory to 1/3, according to Toshiba's estimate. The contribution of the normally-off operation and that of the improvement of the memory element are almost the same, the company said.
Toshiba also announced the results of a simulation for realizing a processor by using the new technologies. With an ARM core and Linux OS, it is possible to reduce power consumption to 1/3 that with a processor using an SRAM cache at the time of using an application while keeping the speed performance, according to the results.
Toshiba will announce three theses on STT-MRAM at the 2012 IEEE International Electron Devices Meeting (IEDM 2012). The lecture numbers of its reports on the memory element, the entire STT-MRAM and the circuit are 29.4, 11.3 and 10.5, respectively.
The latest results were achieved only by Toshiba, and SK Hynix Inc, which co-develops STT-MRAM with Toshiba, was not involved in the development, Toshiba said. The latest development was conducted in a project that the company carries out with New Energy and Industrial Technology Development Organization (NEDO).