Toshiba's STT-MRAM Expected to Cut Smartphone Power Consumption (page 2)
Though the company did not disclose the details, it said that the improvements were made to the material of the perpendicular magnetic memory element with a width of 30nm and its multilayer structure.
When the energy of the STT-MRAM using the new memory element in operation was calculated in a simulation, it was 46pJ. It is about 1/30 that of a traditional STT-MRAM and 1/3 (or less) that of SRAM, Toshiba said.
Furthermore, Toshiba made improvements to circuits. While its six-transistor SRAM and traditional STT-MRAM cache have a path for leakage current, the company developed a memory circuit that does not have a path for leakage current this time. The memory circuit has a three-transistor/one-MTJ structure and does not cause much leakage current in theory like DRAM, the company said.
As a result, it becomes possible to reduce the power consumption of cache memory to 1/3, according to Toshiba's estimate. The contribution of the normally-off operation and that of the improvement of the memory element are almost the same, the company said.
Toshiba also announced the results of a simulation for realizing a processor by using the new technologies. With an ARM core and Linux OS, it is possible to reduce power consumption to 1/3 that with a processor using an SRAM cache at the time of using an application while keeping the speed performance, according to the results.
Toshiba will announce three theses on STT-MRAM at the 2012 IEEE International Electron Devices Meeting (IEDM 2012). The lecture numbers of its reports on the memory element, the entire STT-MRAM and the circuit are 29.4, 11.3 and 10.5, respectively.
The latest results were achieved only by Toshiba, and SK Hynix Inc, which co-develops STT-MRAM with Toshiba, was not involved in the development, Toshiba said. The latest development was conducted in a project that the company carries out with New Energy and Industrial Technology Development Organization (NEDO).