Toshiba Plans to Ship Samples of 3D NAND Flash, ReRAM in 2013
Toshiba Corp had a briefing on its research and development strategies July 10, 2012.
Toshiba plans to increase the number of researchers in its overseas bases by 750 by fiscal 2014, expecting about 5,000 researchers in the overseas bases and about 8,500 in domestic bases in fiscal 2015. According to its medium-term management plans, the company intends to put its energy into the fields of storage and energy. And, this time, the company explained the efforts that it is making in the two fields.
As for the NAND flash memories for storage devices, Toshiba is currently mass-producing 19nm products. And it plans to release new memories having a three-dimensional structure while scaling down the existing NAND flash process technology to its limit.
Toshiba deals with two kinds of memories having a three-dimensional structure: the "BiCS" NAND flash memory and ReRAM (resistive random-access memory). For the BiCS, the company has already developed a technology that realizes a memory hole diameter of 50nm and 16 layers of stacked cells.
"When more than 15 layers are stacked, it becomes possible to realize a cost lower than that of the existing NAND flash," said Masaki Momodomi chief engineer at the company's Semiconductor & Storage Products Co.
Toshiba plans to ship 128-Gbit or 256-Gbit prototype samples (PTSes) in 2013 and engineering samples (ESes) in 2014 and start volume production in 2015. The company intends to realize a 512-Gbit product in 2015 and continue the development in the aim of realizing 1 Tbit or higher capacity.
As for the ReRAM, Toshiba showed a picture of a 64-Gbit test chip. The company plans to ship its samples and start volume production at almost the same timings with the BiCS. Commenting on the capacity of the ReRAM, Momodomi said, "We aim to realize a capacity that is slightly less than or equivalent to the capacity of the BiCS."
Because ReRAMs enable to rewrite data at high speeds, the company intends to use the ReRAM for performance-oriented storage devices. Toshiba is also engaged in the development of STT-MRAM (spin transfer torque MRAM), planning to use it for cache memories including SSDs.
At the same time, Toshiba will scale down its process technology for NAND flash memories having a two-dimensional structure, planning to ship samples of 1Ynm products in 2012 and 1Znm products in 2013.
"We believe that we can go one generation further than that," Momodomi said.
About EUV lithography, he said, "We want to use it as soon as it becomes available." He also said that the company will consider participating in the co-investment program announced by ASML (Press release).