[ISSCC] SanDisk, Toshiba Announce 128Gb NAND Flash Memory

Feb 24, 2012
Motoyuki Oishi, Nikkei Electronics
A picture of the 128-Gbit chip
A picture of the 128-Gbit chip
[ If it clicks, the expanded picture will open ]
The major specifications of the 128-Gbit product
The major specifications of the 128-Gbit product
[ If it clicks, the expanded picture will open ]

SanDisk Corp and Toshiba Corp announced a 128-Gbit NAND flash memory made by using 19nm 3bit/cell technology at ISSCC 2012 (thesis number 25.8).

This is the first time that a 128-Gbit NAND flash memory has been announced at ISSCC. The chip area of the memory is 170.6mm2.

"By using 3bit/cell technology, production cost can be reduced by 20 to 30%, compared with 2bit/cell products using the same technology node," the companies said.

As an input/output interface, the NAND flash memory supports 400Mbps toggle mode. The data transmission rate for writing is 18MBps, which is the highest level in the industry, they said.

"With the writing speed of 18MBps, the new 3bit/cell product can be applied to many applications using NAND flash memories," the companies said.

The page size and power supply voltage of the memory are 16 Kbytes and 2.7-3.6V (input/output voltage: 1.8V), respectively.

For large-capacity storage devices such as SSDs (solid state drives), many NAND flash memory chips have to be operated at the same time to improve the writing performances of the devices. It is possible that the temperatures of memory chips in an SSD rise due to ultra-high-speed writing because many memory chips are often stored in limited spaces for an SSD.

Therefore, SanDisk and Toshiba mounted a digital temperature sensor on the memory chip to control the temperature so that it does not exceed the operating temperature range. A memory controller reads temperature information and controls the access performance to memory based on the information.

When 19nm process technology and 3bit/cell technology are applied, the interference between floating gates becomes even more problematic. Therefore, the companies used an air gap between word lines to reduce the interference between adjacent cells. Also, to reduce chip area, they made improvements to the ABL (all bitline) architecture as well as the charge pump.

According to SanDisk, the shipment of the 128-Gbit NAND flash memory made by using 3bit/cell technology started in the latter half of 2011, and it is currently being mass-produced. The company has already applied a 3bit/cell 64-Gbit product, which was derived from the 128-Gbit chip, to microSD memory cards.

When the latest chip is compared with the 2bit/cell product (memory capacity: 64 Gbits) that is made by using 24nm process technology and was announced by SanDisk at ISSCC 2011, which took place in February 2011, a steady advancement can be seen.

The chip area and writing speed of the 2bit/cell product were 151mm2 and 14MBps, respectively. And its memory density was about 423 Mbit/mm2. The memory density of the latest 3bit/cell product (128 Gbits) is about 750 Mbit/mm2, which is about 77% higher than that of the 2bit/cell product.