[ISSCC] Samsung Announces 4Gb LPDDR3 SDRAM

Feb 22, 2012
Motoyuki Oishi, Nikkei Electronics
The 4-Gbit LPDDR3 DRAM
The 4-Gbit LPDDR3 DRAM
[Click to enlarge image]
The architecture of the DRAM
The architecture of the DRAM
[Click to enlarge image]

Samsung Electronics Co Ltd announced its LPDDR3 SDRAM, which is expected to be the next-generation low-power-consumption DRAM, at ISSCC 2012 (lecture number: 2.4).

"It will be the mainstream DRAM for smartphones this year," the company said.

The capacity of the LPDDR3 SDRAM is 4 Gbits, and it is manufactured by using 30nm process technology. Its power supply voltage is 1.2V. Its maximum data transmission rate per terminal is 1.6Gbps. Because its bus width is 32 bits, the maximum data transmission rate of the entire chip is 6.4GBps. This is the first time that an LPDDR3 product has been announced at ISSCC.

The LPDDR2, which is used for existing smartphones, has a maximum data transmission rate of 800Mbps per terminal. And the maximum data transmission rate of the entire chip is 3.2GBps (when its bus width is 32 bits). Its power supply voltage is 1.2V. In other words, Samsung doubled the maximum data transmission rate per terminal without changing the power supply voltage.

The chip area of the 4-Gbit LPDDR3 SDRAM is 82mm2. It has a backward compatibility with LPDDR2 DRAM. It consists of eight banks and has eight prefetches. Samsung doubled the inner data bus width, compared with that of the LPDDR2, to enhance speed and concentrated terminals on the die (on die termination: ODT) to improve single integrity.

According to Samsung, there are increasing demands for higher-speed mobile DRAMs for 3D gaming and high-definition video. On the other hand, power consumption cannot be increased because of the limitation in power budget.

To achieve a higher speed and a low power consumption at the same time, DRAM makers are considering methods of drastically improving data transmission rate per terminal and drastically increasing the number of terminals. The former method means the employment of Serial IO, and the latter means the introduction of 2-channel applications or Wide IO.

Samsung said that the power efficiency of Serial IO is lower than that of the LPDDR2. As for Wide IO, the company said that it makes failure analysis (modeling of SiP) difficult and increases costs because of the low yield rate in the lamination process. Therefore, Samsung considers that the LPDDR3 is a promising next-generation DRAM.