Hynix Announces 1Xnm-generation NAND Flash Memory Technology

Dec 8, 2011
Jyunichi Oshita, Nikkei Electronics
A cross-section picture of the newly developed cell array
A cross-section picture of the newly developed cell array
[Click to enlarge image]

Hynix Semiconductor Inc of Korea announced "Middle-1Xnm"-generation NAND flash memory technology at IEDM (IEEE International Electron Devices Meeting).

The company reduced the half pitch of the smallest word line to 1Xnm by repeating spacer process technology, which is a kind of double patterning technologies, twice.

This is the first time that 1Xnm-generation NAND flash memory technology has been announced at IEDM. It seems that "Middle-1Xnm" means about 15nm and that Hynix is planning to start volume production in the latter half of 2012.

This time, Hynix developed process technologies to solve problems that are caused by the reduction in size in the directions of the word line and bit line when the generation of NAND flash memory is switched from 20nm to 1Xnm.

Word line direction

In the direction of the word line, the space in which the control gates made of polycrystalline silicon are embedded becomes extremely small. As a result, holes are formed on the control gates, and the gates are depleted, causing more interference between bit lines.

To solve this problem, Hynix added a process that reduces the width of the floating gate in the direction parallel to the word lines and increased the space in which the control gates are embedded. As a result, the interference between bit lines was decreased by 20%.

Bit line direction

In the direction of the bit line, when data is being written, a high electric field is applied between the control gate, to which a writing voltage is applied, and the floating gate, which is located next to the control gate. As a result, electric charge is more likely to leak from the floating gate. To solve this problem, Hynix developed two measures.

First, the company improved the formation process for the air gap that is located in the insulating film and separates adjacent word lines. With a structure in which air gap occupies 50% or more of the space between adjacent word lines, the electric field applied between the control gate and the floating gate next to it at the time of writing data was reduced by 20% compared with a case where there is no air gap.

The air gap also reduces capacity in the direction of the word line and increases the coupling ratio of the control gate and the floating gate.

Second, Hynix reduced the problematic electric field by applying a voltage about 2V higher than the pass voltage to the word line located next to the word line to which a writing voltage is applied at the time of writing data. This method also contributes to increasing data writing speed.

Furthermore, Hynix reduced reading current and leak current in non-selected blocks by making improvements to the source-drain junctions of the cell transistor and selection transistor. The company prototyped a memory cell by using those technologies and confirmed that multi-value operation (2 bits per cell) is possible with enough margin.