[Interview] Intel on 15nm, Beyond CMOS Technologies

Aug 12, 2010 21:28 Jyunichi Oshita, Nikkei Electronics

The limit of scaling down CMOS transistors, which are elementary elements of chips, has long been pointed out. But it seems that the limit still cannot be seen.

For example, in this summer, Taiwan Semiconductor Manufacturing Co Ltd (TSMC) will start constructing a new plant that can mass-produce up to 7nm-node products. TSMC is the only company in the semiconductor industry that announced when to start volume production of 20nm-node products (the latter half of 2012), strengthening its presence in the competition of downscaling.

However, in terms of downscaling, Intel Corp is still in an impregnable position. According to the roadmap of Intel, which advances the generation of CMOS technologies in every two years, the company plans to start volume production of its 22nm-node products in the latter half of 2011. In regard to CMOS technologies, companies in the semiconductor industry seem to use planar CMOS technologies that use high-dielectric (high-k) gate insulating film/metal gate for 22 to 20nm products.

Then, what will CMOS technologies be like in and after the 15nm generation? We asked this question to Kelin J Kuhn, Intel Fellow, Director of Advanced Device Technology, Portland Technology Development. She led the development of 90nm, 45nm, 22nm and 15nm process technologies at Intel and is currently engaged in the development of the 11nm CMOS process technologies.

Q: First of all, we would like to know your perspective on future technologies. When do you think the downsizing of CMOS process technologies will come to an end?

The downsizing will still continue for a long period of time. It will not stop in a short period of time like two, three or five years.

So far, people who pointed out the limit of downscaling have always cited certain technological issues. For example, it is not possible to expose circuit patterns whose line width is smaller than the wavelength of light, and there is a physical limit of the thickness of a gate insulating film.

The semiconductor industry has always come up with clever solutions to such problems as technology generations regarded as limits approach. As for lithography, the solutions were OPC (optical proximity correction) and RET (resolution enhancement technique). And the solution to the issue of gate insulating film was the high-k technology.

Even my former boss, who is now retired, once told me, "The downscaling of CMOS process technologies might come to an end until you retire." Though I was given a plausible reason, it did not happen.

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