[VLSI] Hitachi, Tohoku Univ Announce Multi-level Cell SPRAM

Jun 23, 2010
Motoyuki Ooishi, Nikkei Electronics
Two TMR elements are stacked
Two TMR elements are stacked
[Click to enlarge image]
Four-value operation
Four-value operation
[Click to enlarge image]

Hitachi Ltd and Tohoku University announced a spin-transfer torque memory (SPRAM) in which data can be written by using multi-level cell (MLC) technology.

The announcement was made at the 2010 Symposium on VLSI Technology, an international conference on semiconductor manufacturing technologies that took place from June 15 to 17, 2010, in Honolulu, Hawaii (lecture number: 5.1).

By three-dimensionally stacking two TMR elements and connecting them in series, four-value memory (2 bits per cell) was realized. Hitachi and the university prototyped a memory cell and confirmed four-value operation with spin transfer torque magnetization reversal.

At first, Hitachi planned to replace DRAMs with SPRAMs. But, because of the development of the MLC SPRAM, the company is now considering to use SPRAMs in place of flash memories, the company said.

The two TMR elements have the same composition and thickness of laminated film. Therefore, there is no difference in the density of threshold current (Jc) and magnetoresistance (MR) ratio between the two elements. The only difference is the area in the horizontal direction.

As a result, the value of threshold current (Ic) and the resistance variation (ΔR) are different between the upper and lower TMR elements. For example, when the area of the lower TMR element becomes twice as large as that of the upper TMR element, Ic doubles and ΔR halves. By using these characteristics and optimizing the current value for writing data, MLC operation is realized.

This time, Hitachi and Tohoku University developed two-step writing and reading methods for the MLC SPRAM. The read time of the MLC SPRAM is equivalent to that of single-level cell (SLC) SPRAMs, they said.

The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.

"The number of manufacturing processes to form one TMR element is less than 5% of the number of all the manufacturing processes for SPRAMs," the company said.

With the MLC SPRAM (2bits per cell), it is possible to reduce the effective area of memory cell per bit to less than 4F2 by enhancing the MR ratio. The MR ratio of the TMR element prototyped by Hitachi and the university is about 128%.

"When the MR ratio is as high as 128%, MLC operation can be realized with a memory cell area of about 3.65F2 per bit," the company said.

Hitachi said that it is theoretically possible to realize 3bit-per-cell (eight-value) operation by stacking three TMR elements and that stacking three TMR elements is not very difficult in terms of manufacturing technologies.