[VLSI] Toshiba, et al Develop '3D FPGA'

Jun 21, 2010 18:54 Motoyuki Ooishi, Nikkei Electronics

Toshiba Corp realized a so-called "3D FPGA" by three-dimensionally stacking SRAMs based on amorphous silicon (Si) TFT technology on a CMOS logic circuit in collaboration with Covalent Materials Corp, Tier Logic Inc and TEI Technology Inc.

The 3D FPGA was announced at the 2010 Symposium on VLSI Technology, an international conference on semiconductor manufacturing technologies that took place from June 15 to 17, 2010, in Honolulu, Hawaii (thesis number: 21.1).

Existing FPGAs have a structure in which logic circuits for user logic and SRAMs for configuration are two-dimensionally arranged. In the case of the 3D FPGA, SRAMs for configuration are formed by using amorphous Si TFT technology and stacked on a nine-layer CMOS chip that has copper (Cu) wiring and logic circuits for user logic. As a result, the chip area of the FPGA can be reduced to about half that of existing FPGAs.

"The 3D FPGA is expected to reduce costs as much as advancing semiconductor manufacturing technologies by two generations," Toshiba said.

With the 3D FPGA, device makers can switch to cell-based chips without making changes to chip designs. Devices are prototyped by using the 3D FPGA. Then, only the amorphous Si TFTs on which SRAMs for configuration are formed are replaced with mask ROM so that cell-based chips can be obtained without redesign.

This time, the four companies prototyped a chip by stacking 26-Mbit SRAMs based on amorphous Si TFT technology on a foundation layer made by using 90nm-node nine-layer Cu wiring technology. The foundation layer of the prototyped chip is made with 90nm CMOS technology, but Toshiba said, "We consider it possible to use 40nm technology."

24 Hours | 7 Days