TSMC Draws Roadmap to 20nm Process

Feb 26, 2010 20:40 Kyoumei Nagahiro, Tech-On!

Taiwan Semiconductor Manufacturing Co Ltd (TSMC) hosted the TSMC 2010 Executive Forum on Leading Edge Technology Feb 24, 2010, in Yokohama, Japan.

Shang-Yi Chiang, the company's SVP of R&D, delivered a lecture on technology development, etc. He spoke on the individual process technologies that will be introduced for the 45/40nm, 32/28nm and 22/20nm processes and explained about the current status of each process.

45/40nm process

The new technologies introduced for the 45/40nm process are ArF immersion exposure, the third-generation strained silicon and a low-k interlayer insulating film whose dielectric constant was lowered to 2.5. Though TSMC had a difficult time developing technologies for the 45/40nm process at first, it has solved problems and is now rapidly establishing the technologies.

The defect density was reduced to 0.1-0.3/(inch)² in the third and fourth quarters of 2009. The number of tape-outs increased at a rapid rate, and half of the taped-out chips are now being mass-produced, TSMC said.

32/28nm process

The most important new technology for the 32/28nm process is a new gate. A SiON gate insulating film is used for the low-power type (28LP) while a high-dielectric gate insulating film and a metal gate electrode (high-k/metal gate) are used for the high-performance type (28HP) and the medium-speed, low-leakage type (28HPL).

As a process to form the high-k/metal gate, TSMC employed the gate-gate-last process instead of the gate-first process, which the company was planning to use at first. Also, it will introduce the fourth-generation strained silicon and low-resistance Cu wiring. The company lowered the resistance of Cu wiring by improving the flatness of the boundary surfaces of the Cu and barrier metal to prevent electrons flowing on the surface of the wiring from scattering.

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