[IEDM] Japanese Researchers Develop SRAM Operating at 0.5V

Dec 11, 2009 12:00 Jyunichi Ooshita, Nikkei Microdevices & Motoyuki Ooishi, Nikkei Electronics

The University of Tokyo and Japan's National Institute of Advanced Industrial Science and Technology (AIST) developed an SRAM that operates at as low a voltage as 0.5V.

The new SRAM has a power consumption 32% lower than existing SRAMs while its cell area is not larger. It was realized by replacing six MOSFETs that constitute an SRAM with ferroelectric FETs, which are made by inserting a ferroelectric substance at the gate of a MOSFET.

The research was conducted by a group led by Ken Takeuchi, associate professor of the School of Engineering at the University of Tokyo, and the Frontier Device Group of Electronics Research Department at AIST (group leader: Shigeki Sakai).

This time, it was proved by theoretical calculation that the window of (permissible variation in) the threshold voltage of transistors constituting an SRAM can be widened by using ferroelectric FETs. As a result, it became possible to lower the operating voltage of SRAM from 0.61V, which had been the lower limit, to 0.5V, reducing the power consumption of SRAM by 32%.

The window of the threshold voltage can be widened by using ferroelectric FETs because the threshold voltage of the ferroelectric FETs is automatically adjusted in the direction where written data becomes stable. This phenomenon is caused by the fact that the threshold voltage of the ferroelectric FETs fluctuates based on the polarization direction determined by the properties of the gate voltage.

In the case of the nMOS, when the polarity of the gate voltage is positive, the threshold voltage is low. And, in the case of the pMOS, this relationship reverses.

When datum "0" is written in the new SRAM, a positive gate voltage is applied to the nMOS and the pMOS on the side of the data retention node, lowering the threshold voltage of the nMOS and raising the threshold voltage (absolute value) of the pMOS. As a result, the on-state of the nMOS and the off-state of the pMOS are stabilized, preventing the phenomenon that retained data is inverted due to the variation in the threshold voltages of the nMOS and the pMOS.

The same mechanism works on the other data node. And, when datum "1" is written, data is automatically stabilized as well.

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