[IEDM] Univ of Tokyo, Others Realize CMOS Device Using 7-micron Wafer

Dec 10, 2009 12:02 Satoshi Okubo, Nikkei Microdevices

The Institute of Engineering Innovation of the School of Engineering at the University of Tokyo developed a technology to reduce the thickness of a 300mm wafer (silicon substrate) to 7μm in collaboration with Disco Corp, Dai Nippon Printing Co Ltd, Fujitsu Laboratories Ltd and WOW Research Center Ltd.

For example, it is possible to realize a 1.6-Tbyte memory module with a package size as small as a thumb by using the new technology to stack 100 layers of 16-Gbyte memory chips and connect them with through-silicon via (TSV) technology.

The institute and the four companies made a presentation on the new technology at IEDM 2009, an international conference on semiconductor manufacturing technologies. Specifically, a 45nm CMOS device for a CMOS logic device was formed on a silicon wafer. And, when the thickness of the wafer was reduced to 7μm, it did not affect the strained silicon, copper wiring or low-k interlayer dielectric film of either the n-type MOSFET or the p-type MOSFET.

The transistor characteristics did not deteriorate. And this is the first time that the thickness of a 300mm wafer has been reduced to 7μm and its properties have been evaluated.

This time, it was conducted by the WOW alliance, an industry-university alliance promoted by Takayuki Ohba, specially appointed professor of the Institute of Engineering Innovation. The alliance consists of about 20 companies.

The new technology is expected to be used to reduce the thickness of a wafer on which a CMOS device is formed, stack the thinned waters and interconnect them with TSV technology in the aim of increasing the mass productivity of 3D-stacked chips. The costs of the new method, in which 3D-stacked chips are cut out of stacked wafers, are lower than those of the method of stacking semiconductor chips cut out of a wafer or staking chips on a wafer to make a 3D-stacked chip.

Thus far, the thickness of wafer has been reduced to about 20μm. The thickness of 7μm makes it easy to form TSVs as well as to embed metal in TSVs, further reducing the manufacturing costs, the institute said.

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