Two short courses were held Dec 6, 2009, which is the day before the opening of IEDM 2009, an international conference on semiconductor manufacturing technologies.
One is titled "Scaling Challenges: Device Architectures, New Materials, and Process Technologies" and focused on semiconductor microfabrication technologies. And another is titled "Low Power/Low Energy Circuits: From Device to System Aspects," which is about low power consumption technologies.
In the former short course, Ghavam G Shahidi of IMB Corp's Research Division delivered a lecture titled "Device Architecture: Ultimate Planar CMOS Limit and Sub-32nm Device Options." He said that the scaling of devices can reach 15nm, 11nm and beyond with silicon.
"Though it is possible to go beyond 11nm with silicon, it is necessary to drastically change existing device architectures and to thoroughly employ fully-depleted transistors," Shahidi said. "Specifically, FinFet, ETSOI (extremely thin SOI) and nanowires have to be used."
In that case, the voltage of silicon transistor will possibly settle at about 0.6V from the viewpoint of power density, he said. Furthermore, it is possible to employ higher mobility substrates to realize a frequency higher than silicon trend and a lower power consumption.
In the 15nm and 11nm generations, device performance is not much improved by microfabrication than in the 32nm and 22nm generations, Shahidi said.
"(In the 15nm and 11nm generations,) we will reduce energy consumption per performance in every generation by scaling the gate length and width of transistor and its voltage," he said.
Also, Shahidi expects that the number of elements per semiconductor chip will drastically increase in the next ten years.
"We will soon see a chip with 50 to 100 billion elements," he said.
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