Japanese Venture Provides Real-time OS as Hardware

Sep 25, 2009
Tomonori Shindou, Nikkei Electronics
A board with the evaluation chip
A board with the evaluation chip
[Click to enlarge image]
A demonstration of transferring a file via network
A demonstration of transferring a file via network
[Click to enlarge image]
The CPU load of the host device. The left and center curves were recorded when the "Artesso" was being used. And the right curve was recorded when software was run without using the Artesso.
The CPU load of the host device. The left and center curves were recorded when the "Artesso" was being used. And the right curve was recorded when software was run without using the Artesso.
[Click to enlarge image]

Netcleus Systems Corp, a Japan-based venture firm, prototyped an LSI chip based on the "Artesso," a technology to provide a real-time operating system (OS) as hardware, enhance the response of application programming interfaces (APIs) and lowers power consumption.

The company developed the technology in 2008 and has since used it with an FPGA (field programmable gate array). But, this time, it developed an evaluation chip by using 90nm technology.

The Artesso can accelerate, for example, protocol processing that heavily uses OS's APIs by 15 times or more compared with the case where software is run on a general embedded CPU core. If the performance is the same, it contributes to reducing power consumption.

The real-time OS "μITRON" was provided as the hardware. Many of the variables and data structures used by the OS exist in registers so that common OS processes such as waking up tasks, semaphore waits and receiving e-mail can be completed within 10 clocks, which is about 1/100 the time software processes take.

The acceleration of an entire application depends on the rate at which the OS uses APIs. In TCP/IP protocol processing, which Netcleus Systems assumes, the rate is high. With the evaluation chip, the effective throughput of TCP/IP and power consumption were 500Mbps and about 300mW, respectively, at 150MHz operation. In the case of normal embedded CPU cores, the effective throughput is about 30Mbps at 150MHz operation.

According to Netcleus Systems, it is technically possible to support real-time OSes other than μITRON such as "OSEK" and protocols other than TCP/IP.

To process TCP/IP transactions, it is necessary to rearrange header information. And the prototyped LSI chip is mounted with hardware to carry out the rearrangement.

At first, the LSI chip will be aimed at applications such as improving the throughput of network devices and lowering the power consumption of multifunction machines. Netcleus Systems is considering offering an IP core with the same function. The size of the logic circuit (without RAM) is several hundred thousands of gates or less.