[VLSI] Toshiba Announces 32Gb 3D-stacked Multi-level NAND Flash
Toshiba Corp developed the "P-BiCS (Pipe-shaped Bit Cost Scalable)," a 3D-stacked NAND flash memory, with 2bit/cell multi-level cell technology at the 2009 Symposium on VLSI Circuits (lecture number: 7-1).
It prototyped a 32-Gbit chip by stacking 16 levels of memory cells developed using 60nm process technology and confirmed its array operation. The chip measures 10.11 x 15.52mm, and the chip area is 6F2 (F: design rule). The effective cell area per bit is 0.00082μm2, which is smaller than that of the 32nm NAND flash memory to be rolled out by the company in 2009.
Multi-level operation, verification of operation at an array level
The P-BiCS is the advanced version of the "BiCS," a 3D-stacked NAND flash memory Toshiba has been developing since 2007. The BiCS uses a technology to stack memory cells in multiple levels by (1) stacking a gate electrode film and an interlayer dielectric film alternately, (2) making a hole that passes through all the layers and (3) embedding a polycrystalline Si channel.
This time, the company changed the shape of the NAND string to enable multi-level operation and verify the operation at an array level.
While cells are connected to a linear (I-shaped) NAND string in the BiCS, a U-shaped NAND string is used for the P-BiCS. There are two major advantages to this structure.
Properties improved by reshaping NAND string
First, because the quality of the memory cell's tunnel insulating film is enhanced, operation window and data retention capability are improved, realizing the multi-level operation. The quality of the tunnel insulating film is improved because the process of removing the tunnel insulating film at the bottom of the through-hole becomes unnecessary.
In the BiCS, the tunnel insulating film formed on the wall on the side of the through-hole is damaged during this process, often deteriorating the memory property.
Toshiba announced the method of reducing the damage by changing the material of the tunnel insulating film from SiO2 material to SiN material at the 2007 IEDM. However, the company could not ensure a sufficient memory property with the SiN material, it said.
Second, because the properties of the selection transistor and the source line used to read/write data are improved, the operation property at the array level is bolstered. In the BiCS, which has an I-shaped string, a selection transistor and a source line have to be placed on the lower part of the string.
On the other hand, in the P-BiCS, whose string is U-shaped, they can be arranged at the end (upper part) of the string. Therefore, when the string is being formed, heat of nearly 1,000°C is not applied to the selection transistor or the source line. As a result, the cutoff property of the selection transistor is enhanced, decreasing the number of read errors.
Because metal materials can be used for the source line, the writing speed can be faster than that of the BiCS. The BiCS uses a diffusion layer, which tends to be highly resistive, as a source line. When the resistance of the source line is high, the variation in threshold voltage becomes larger in the array, lowering the writing speed.
Mass production process required
The development group of the P-BiCS aims to establish a mass production technology for 3D-stacked NAND flash memory in two or three years as a measure to highly integrate NAND flash memory without relying on microfabrication. The P-BiCS seems to be one of the major candidates for that purpose.
"One more breakthrough is required in the processes of stacking cells and opening the through-hole to lower the cost," Hideaki Aochi, chief specialist, Advanced Memory Device Technology Dept, Center for Semiconductor Research & Development, Toshiba Corp.
For example, the hole can currently be opened through about eight levels at the same time. And the 16 levels are realized by stacking eight levels of cells twice. In the future, Toshiba might have to develop a process to form more than 16 levels at once.