[VLSI] 'Digital Rosetta Stone' Passes Down Cultural Heritage to Future Generations

Jun 18, 2009
Masahide Kimura, Nikkei Electronics
The concept of "Digital Rosetta Stone (DRS)"
The concept of "Digital Rosetta Stone (DRS)"
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The prototype test chip
The prototype test chip
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The slate was provided with 56mW power.
The slate was provided with 56mW power.
[ If it clicks, the expanded picture will open ]

Japanese researchers prototyped a memory system that can store large volumes of data for more than a thousand years.

The system, "Digital Rosetta Stone (DRS)," was announced June 16, 2009, by Keio University, Sharp Corp and Kyoto University at the 2009 Symposium on VLSI Circuits, which is taking place in Kyoto, Japan (lecture number: C3-3). They stacked wafers mounted with mask ROM and packaged it with SiO2. Power supply and signal communication are conducted by wireless.

To store various cultural heritage that has so far been created by mankind as digital information and hand it down to posterity, it is necessary to develop a memory system that can store data for more than a thousand years and has a capacity of 1 Tbit or more and a data access speed of 100Mbps or more, according to the researchers.

In the case of HDDs, data could be lost in four to 40 years due to the influence of magnetic field. And data stored in an optical disc could be lost in 30 to 100 years when affected by oxygen or moisture. On the other hand, semiconductor devices can keep data intact for a thousand years or more if the humidity around the chip is kept at 2% or less.

Thus, the researchers proposed the idea of saving data on the mask ROM with electron-beam direct-writing technology, stocking the wafers and packaging them with SiO2 to form a "slate." When a wafer (reader) for reading data is attached to the slate, it becomes possible to supply power and communicate signals by wireless.

If four 15-inch wafers made by using 45nm CMOS technology are stacked, the memory capacity will be 2.5 Tbits.

This time, the researchers utilized 0.18μm CMOS technology and prototyped test chips corresponding to the slate and the reader. The size of the test chips is 5 x 5mm. The diameter of the inductor is 2mm for power supply and 0.4mm for data communication. And the capacity of the mask ROM is 1 Mbit.

They succeeded in providing 56mW power to the slate by four-channel wireless transmission when the distance between the slate and the reader is 0.2mm. By this method, a data transmission speed of 150Mbps can be realized.