[VLSI] NEC Develops Technology to Slash Write Current of Embedded MRAM
NEC Corp and NEC Electronics Corp developed a technology to reduce write current by 90% for embedded MRAMs.
The technology can be applied to embedded memories of advanced SoCs (system on a chip). In addition, when used for the register of a logic circuit, it can realize an SoC that consumes no standby power.
So far, NEC and NEC Electronics have developed other technologies that enhance the operational speeds of embedded MRAMs. But the companies used the "current magnetic field write method," in which data is written by the magnetic field induced by electric current, resulting in a write current as high as several milliamperes. And this method increases the write current as microfabrication proceeds, making it difficult to apply the method to advanced SoCs.
To address such problems, NEC and NEC Electronics employed a new method called "spin torque domain wall displacement write method" to reduce write current and realize microfabrication at the same time. In addition, they used a test chip to confirm that it is possible to lower the write current to 0.2mA or less.
In general, an MTJ (magnetic tunnel junction), an elementary element of MRAM, has the value of 0 or 1 depending on the magnetization direction of the free layer. In the spin torque domain wall displacement write method, a magnet is placed on each edge of the free layer so that two magnetization directions become opposite to each other.
As a result, a "magnetic wall," at which the magnetization direction drastically changes, is formed in the middle of the free layer. At this point, when write current is applied along the free layer, the magnetic wall moves from side to side depending on the direction of the electric current, switching the value of the magnetization direction between 0 and 1.
The strength of electron interaction (spin torque) needed to move the magnetic wall varies depending on current density. Therefore, as the size of the element decreases, the write current can be smaller.
NEC and NEC Electronics announced the concept of the technology in June 2007. But, this time, they verified the operation of the test chip. Also, they utilized perpendicular magnetization instead of in-plane magnetization, in which magnetization direction is switched in the in-plane direction of the free layer. As a result, it became possible to rewrite data with a lower write current density even if a highly coercive material is used for the free layer.
Furthermore, in perpendicular magnetization, the width of the magnetic wall can be about 10% of that required in in-plane magnetization, making it easier to downsize the element. The movement speed of the magnetic wall is as fast as 50m/s. When the size of the free layer is 100nm, an operation speed equivalent to 500MHz is expected to be realized. The electromagnetic material used in the free layer is a CoNi multilayer film.
This time, the test chip was manufactured using 150nm CMOS process technology, but NEC and NEC Electronics plan to scale down the chip to 55nm or 40nm and verify its operation. They aim to complete the new technology within 2010. And the technology will be transferred to NEC Electronics, which intends to commercialize it.
The details of the technology will be announced at the 2009 Symposium on VLSI Technology under the title "Low-current Perpendicular Domain Wall Motion Cell for Scalable High-speed MRAM" (lecture number: 12A-2).