Toshiba Corp showcased a 300mm wafer integrating 32nm NAND flash memory chips at the International Nanotechnology Exhibition & Conference (nano tech 2009), which took place from Feb 18 to 20, 2009.
It is a 32-Gbit product based on the 3-bit per cell technology, and volume production is scheduled for September 2009.
Commenting on the device structure in the 32nm node, Toshiba said, "We didn't make any significant changes from the (previous) 43nm node." The new wafer uses a floating gate structure as before (Press release).
However, in the 32nm node, the number of stored electrons per floating gate is reduced to about 200, according to the company. As a result, when the threshold voltage is divided in eight to realize 3-bit per cell, the write margin becomes extremely small. To cope with this problem, the company "made a major improvement to the circuit," it said.
Toshiba has announced this circuit technology at International Solid-State Circuits Conference (ISSCC) 2009.
In regard to the technology for 2X-nm node devices that the company plans to mass-produce from late 2010 or 2011, it is currently "trying to determine whether the floating gate structure can still be applied or a new structure like a nitride trap (MONOS) will be required," the company said.
Many pointed out that the floating gate structure would reach its limit in the 3X-nm node or earlier due to, for example, inter-cell interference. But Toshiba is still exploring the possibility of applying it to the 2X-nm node. Judging from the mass-production schedule, the company is likely to make a decision on this matter at an early date.
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