[ISSCC] Wireless Technology Helps Make Micro SSD Using 64 NAND Chips
Keio University and its partners announced an inductive-coupling wireless communication technology to realize an SSD composed of three-dimensionally layered 64 NAND flash memory chips at ISSCC 2009.
SSDs developed by using this technology will reduce power consumption of the system to 1/2, the number of loaded LSI packages to 1/8 and the area of communication circuits to 1/40 compared with existing SSDs. The new SSD was realized by multi-layering 64 NAND flash memory chips inside one LSI package and using inductive coupling for wireless communication between the memory chips.
This technology was developed by a research group led by Tadahiro Kuroda, professor of the Department of Electronics and Electrical Engineering at Keio University. The paper on the technology was published jointly with the University of Tokyo.
Keio University and its partners propose a so-called micro SSD composed of a single LSI package. The SSD incorporates 64 NAND flash memory chips inside one package. If the 64 chips are incorporated in an SSD using existing methods, more than 1,500 wires have to be installed inside the package, according to the research group.
By using the new wireless communication method, on the other hand, the number of wires inside the package can be reduced to 200 or less. Data communication between memory chips and the controller can be carried out in the form of inductive-coupling wireless communication. Wires are used for power supply, grounding and control.
Three major modifications were made to layer 64 memory chips. First, a shield was used for relay transmission of information between the chips. Each of the memory chips is equipped with an inductive coupling repeater, and data is communicated via relay transmission between the chips.
The relay transmission was made possible by setting a metal pad shield at an appropriate position of each chip, utilizing the phenomenon that magnetic flux is attenuated by shields. And It was confirmed that signals and crosstalk are reduced as expected.
Second, a state machine was developed so that chips can be selected without giving individual numbers to them.
"It is especially important for an SSD, in which identical chips are layered," Kuroda said.
This state machine can be easily developed using existing circuit technologies, he said.
Third, a packet communication method was employed for memory access so as to allow communication using existing memory circuits. The area was reduced by adopting multiplex communication system and sharing control signals and data.
The group prototyped the chips using 180nm-generation CMOS technology. Six chips, each 60μm thick, were stacked in layers. Measurement results indicated that relay transmission was properly conducted and that the state machine could be set wirelessly, according to the group.