Fisheye Image Processed in Real Time by FPGA

Nov 20, 2008
Mayuko Uno, Nikkei Electronics
The original image is shown on the left display, and the corrected image is on the right.
The original image is shown on the left display, and the corrected image is on the right.
[Click to enlarge image]

Xilinx Inc demonstrated a "fisheye image correction circuit," which corrects images shot by a fisheye lens camera in real-time in accordance with given central coordinates and magnification ratio.

The circuit was embedded on a board equipped with the company's low-priced FPGA (field-programmable gate array), "Spartan-3A," for the demonstration at Embedded Technology 2008, which runs from November 19 to 21, 2008, at Pacifico Yokohama in Yokohama City, Kanagawa Prefecture, Japan.

When combined with a facial recognition function, the new technology can realize a tracking system. The technology was developed by Dainippon Printing Co Ltd, which plans to sell it as an IP core or ASIC (application-specific integrated circuit).

The function to capture wide-field images by using a fisheye lens camera has already been used in ASSPs (application-specific standard products) provided with DSP (digital signal processing) functionality. The price can be lower than existing ASSPs by using a low-priced FPGA (as shown in the demonstration) or integrating it with other image processing circuits into one single ASIC chip, according to Xilinx.

In the demonstration, a 1.3-Mpixel USB camera (15 fps) equipped with a fisheye lens was used. The circular part where images are actually captured features a pixel count of 0.7 million and outputs VGA (video graphics array, 640 x 480 pixels) images at 20 fps.

The "XC3SD3400A," an FPGA with 3.4 million system gates, was used in the demonstration, but the CLB utilization rate was about 20%, according to Xilinx. The company says the rate can be lowered to 15% if the functions are narrowed down, expecting that the circuit can be included in the products with 1.8 million system gates when mass-produced using FPGAs.

The demonstration device can handle image data of four million pixels or less because the memory capacity of the evaluation board is limited. But the correction circuit itself can deal with the input of up to 10-Mpixel image data, according to the company. It is currently developing a circuit for VGA output at 30 fps, responding to demands for smoother images.

The visitors were most interested in the system's use in car-mounted cameras, with some of them asking if they have already been commercialized, Xilinx said. Dainippon Printing also envisions its use in surveillance cameras on streets and video conferencing systems.

Furthermore, Xilinx demonstrated eight-lane PCI Express Gen.2 by using a high-performance FPGA, "Virtex-5 FXT," which includes a 6.5 Gbps serial transceiver. The PCI Express Gen.2, which has a data transmission speed of 5 Gbps, is used for processing full HD images for more than three channels, for example, according to the company. There is an increasing demand for image processing for large security systems composed of 10 to 20 cameras, and the company expects the PCI Express Gen.2 will be used for such purposes.

The eight-lane PCI Express Gen.2 was demonstrated by using an FPGA. The "TB-5V-FX200T-PCIE-EX," an evaluation board manufactured by Tokyo Electron Device Ltd, was used for the demonstration. "We are now ready to make a prototype using FPGA and PCI Express Gen.2," Xilinx said.
The eight-lane PCI Express Gen.2 was demonstrated by using an FPGA. The "TB-5V-FX200T-PCIE-EX," an evaluation board manufactured by Tokyo Electron Device Ltd, was used for the demonstration. "We are now ready to make a prototype using FPGA and PCI Express Gen.2," Xilinx said.
[Click to enlarge image]