Renesas Technology Corp announced its R&D roadmap at a press conference in Tokyo Oct 22, 2008.
Masao Nakaya, board director and executive general manager of Renesas' LSI Product Technology Unit, made the announcement about the company's plan to raise its development efficiency and provide high added-value products by reinforcing its design ability.
First, Nakaya expressed his view on the semiconductor industry. Though it will be difficult to post a 20% growth as in the past, the semiconductor industry will still continue to grow at a rate of 7% to 8%, higher than the overall economy's average growth, he said. Challenges that the industry is facing are declining product unit prices and the increasing ratio of the design cost in the total development cost.
Product unit prices have continued to fall since 1995. Meanwhile, the ratio of the design cost in the development cost is rising fast along with the miniaturization of manufacturing process. In the 0.18μm generation, for example, a manufacturing cost and a design cost were almost equal when one million units of 10 x 10mm chips are manufactured. In the 65nm generation, a design cost jumps up to nearly 10 times the manufacturing cost.
That is because system-level design requires a large amount of human resources (from specification to RTL). In the case of a chip with 180 million transistors manufactured using 90nm process technology, for example, human resources required for system-level design account for 51% of the overall design cost.
With the aim of cutting the system-level design cost by 20 to 30%, Renesas is implementing primarily two measures. One is the creation of virtual hardware models using the C language (or its extension languages). This measure allows the company to start developing software earlier than before as well as to find hardware design errors at an early stage.
The second measure to raise system-level design efficiency is the introduction of a motion synthesizer tool.
"We've already used a motion synthesizer tool circulated in the market in part of our 'VPU' video codec IP core," Nakaya said.
Renesas previously revealed the case of its adopting a motion synthesizer tool manufactured by Cadence Design Systems Inc of the US at an event hosted by Cadence Design Systems, Japan.
Nakaya also introduced the "EXREAL" platform as another measure to increase design efficiency. He explained that Renesas has applied EXREAL to its "RX" CISC microcontroller currently under development. Using EXREAL, the company is aiming at developing ASSPs that use the microcontroller with additional new circuits, as well as making it easier to develop the microcontroller's descendant products.
Renesas intends to boost added-value, the other policy in the roadmap announced this time, primarily through hardware IPs. Specifically, the IPs are (1) multi-core SH microprocessors and processor core technologies such as the abovementioned VPU and the "MX" ultra-parallel processing circuit, (2) analog IPs such as RF circuits and A-D/D-A converters and (3) memory IPs including flash memory and MRAM.
In addition to IP cores, Nakaya cited a network technology that combines security technology and wireless networks as another technology to boost added-value of its products.
At the end of the presentation, he explained about the company's research and development costs, overseas development system and joint development with its partners as its R&D infrastructure. For example, Renesas will continue to invest 15 to 16% of sales in research and development while gradually cutting its capital investment from now on.
The company will increase the number of employees at its overseas development bases from 1,000 in 2007 to 2,000 in 2011. As of March 2008, Renesas has 28,600 employees worldwide, and 20% of them are engaged in research and development.
As Renesas cannot afford all research and development alone by itself, it is conducting joint development with its partners as well. It explained about the joint development of 32nm process technology with Panasonic Corp, which had been announced recently, as a specific example.