Hitachi, University Develops 'Nonvolatile IC'

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Aug 27, 2008 18:56 Megumi Yoshizawa, Nikkei Electronics

Tohoku University's Research Institute of Electrical Communication (RIEC) and Hitachi Ltd prototyped an integrated circuit that integrates an arithmetic function and a nonvolatile memory function by using spintronics and Si technologies.

RIEC and Toshiba made the IC by stacking a magnetic tunnel junction (MTJ) device, one of the spintronics-based devices, onto a Si chip on which a MOS transistor is formed. The structure enhances the data transfer rate between the arithmetic area formed on the Si chip and the memory area, and reduces the IC size.

In addition, because nonvolatile memory can be formed with the MJT device, it isn't necessary to keep the memory on at all times to retain the stored data. Thus, the standby power consumption of the CPU can be reduced to zero, RIEC said.

In the development of the IC, Hitachi formed the MOS transistor on the Si chip, while RIEC stacked the MTJ device on the chip.

In the existing CMOS logic ICs, the arithmetic and memory circuits have to be provided separately from each other. This layout has problems of a considerable delay in data transfer between the arithmetic logic block and the memory block, as well as a heavy power consumption resulting from the delay.

Moreover, a memory circuit combined with a MOS transistor has to be kept on to retain the stored data because a MOS transistor itself has no memory function, according to RIEC. Thus, the existing ICs are faced with problems such as a larger circuit size and a higher standby power due to leakage current.

As an approach to overcome such problems, it has been proposed to adopt the "logic-in-memory architecture," while making the memory block nonvolatile. The logic-in-memory architecture is a scheme to arrange the arithmetic logic circuit and the memory circuit close to each other.

The prototype chip is a full adder composed of the SUM and CARRY blocks. The SUM block measures 15.5 x 10.7μm, and the CARRY block is 13.9 x 10.7μm. The CMOS logic block was formed with Hitachi's 0.18μm process technology.

The paper on this prototype IC was posted in the Aug 22, 2008 edition of the online version of the "Applied Physics Express," a Japanese academic journal of applied physics.

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