Tessolve Adopts Synopsys' Scan Compression Solution to Reduce Test Costs

Aug 30, 2007 10:31 Nikkei Electronics Asia

Tessolve of India has adopted Synopsys Inc's design-for-test (DFT) MAX scan compression solution to reduce the costs of semiconductor testing and diagnostics. DFT MAX creation of scan compression circuits on-chip which decrease the amount of data and time required to test complex ASICs.

Synopsys DFT MAX solution utilizes adaptive scan compression technology to minimize test costs by reducing both test application time and test data volume. By avoiding the use of complex sequential state machines for compression/ decompression, DFT MAX disperses test logic throughout the design, alleviating wire-routing congestion and reducing the silicon area overhead cost of compression.

TetraMAX diagnostics automate failure analysis of manufactured parts by identifying circuits that could contribute to mismatches between expected results generated by the TetraMAX automatic test pattern generator (ATPG) and observed responses of the device under test.

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