Fujitsu Ltd and Fujitsu Laboratories Ltd have announced a platform technology for 45nm LSI logic chips, which combines technologies for low power consumption and high-performance interconnect.
In order to improve LSIs, there are two problems to overcome. First, to shorten the gate length of each transistor so as to make the spaces between interconnects. Second, to minimize the time lag from interconnects between millions of transistors within the LSI chip for higher speed.
Fujitsu researchers used nano-clustering silica (NCS), which has a dielectric constant of 2.25 -- claimed to be the lowest of any insulating film reported to date -- in a lower interconnect region suitable for the smallest interconnect spaces. NCS is an insulating material pocked with miniscule holes, enabling both a low dielectric value and high mechanical strength simultaneously. NCS is used in between different layers instead of an individual layer to further reduce interconnect capacitance.
Compared with previous 45nm technologies on record, the new platform reduces the leakage current that occurs when current is wasted in wait states to one-fifth that of previous levels and reduces interconnect-induced lag times by approximately 14%. The new technology boosts up LSI logic chips with higher speeds, smaller size and lower power consumption.
Nikkei Electronics Asia magazine is available each month free of charge to engineers, managers and other qualified readers.
Nikkei Electronics |
Nikkei Monozukuri |
Nikkei Automotive Technology |
|---|---|---|
 |
 |
 |
| The magazine for electronics designers and managers. | Design You Won't Regret - How to Reduce the Risk of Accidents | The comprehensive automotive technology magazine. |
Copyright © 1995-2010 Nikkei Business Publications, Inc. All rights reserved.
All editorial content and graphics on this Web site may not be reproduced in whole or in part without the express permission of the copyright owner.
February 2010
January 2010
December 2009