Tokyo Univ., Samsung Propose Technology to Ease Reuse of IP Cores Using UML

Jun 5, 2007 18:07 Ikutarou Kojima, Nikkei Microdevices

The EDA-related biggest event 44th Design Automation Conference (DAC 2007) opens on June 4 (local time) in San Diego, California, US. Several workshops were held as a pre-event on Sunday, the day before the opening. The fourth "UML for SoC Design 2007" was held as part of these workshops.

At the UML for SoC Design 2007, the University of Tokyo and Samsung Electronics Co., Ltd. announced achievements of their joint research. The research is an attempt to make it easy to use IP cores using UML. The lecture was entitled "UML-Based Specification Method of Hardware IPs for Efficient IP Reuse." The research team proposed a method to search for and check IPs, based on which it developed a library tool (software).

The method's key feature is that it describes data between IP cores in both XML and UML formats. SPIRIT Consortium's "IP XACT" also uses XML to record IP data, but it "is not really sufficient for chip designers to find a desired IP core from the library, since the technology focuses on information about the IP's structure and connection," said the lecturer Yeonbok Lee from the University of Tokyo.

The newly developed method describes information required to reuse IP cores in the XML format and uses such information for searches and checking. Furthermore, the method describes other information (external functions, internal functions and timing) in the UML format so the designer can thoroughly understand the discovered IP. This is because UML-based graphic information is easier to understand than text.

At the end of the lecture, Lee showed the GUI of a tool based on this method and search results using the tool. Building up a library that manages 1,000 IP cores in a hierarchical structure, the software searched an IP core from the library. The processing time was indicated, but "It is difficult to evaluate this method and tool" as Lee said himself. Results from applying this technology to a library used in actual LSI design processes are hoped for.

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