Fujitsu Introduces Progress in Carbon Nanotube Interconnect Technology

Feb 22, 2007
Masahide Kimura, Nikkei Electronics
Displayed wafer after planarization for the first time
Displayed wafer after planarization for the first time
[Click to enlarge image]
Following last year, the companies presented 300-mm wafer on which CNTs are grown
Following last year, the companies presented 300-mm wafer on which CNTs are grown
[Click to enlarge image]

At "International Nanotechnology Exhibition & Conference" (nano tech 2007), Fujitsu Ltd. and Fujitsu Laboratories Ltd. have introduced its interconnect technology using a carbon nanotube (CNT) being developed by a semiconductor consortium in Japan. Fujitsu aims to commercialize the technology in or beyond 32-nm node.

CNTs can boost an electrical current density by two to three digits compared to Cu, and be applied for precision LSI interconnect. Fujitsu and Fujitsu Laboratories studied CNT technology on their own before, but have transferred and continued its research at Semiconductor Leading Edge Technologies, Inc. (Selete) as part of Japan's national MIRAI project since FY2006. Other than Fujitsu, Toshiba Corp., Matsushita Electric Industrial Co., Ltd., ULVAC, Inc. and Waseda University participate in the research. Slete projects to verify the superiority of via interconnect using CNTs in Phase 1 (FY2006 to FY2007) of the MIRAI 3, and develop a test process using 300-mm wafer in Phase 2 from FY2008 to FY2010.

In the CNT interconnect under development, multi-layer CNTs are grown vertically on a Si substrate through chemical vapor deposition (CVD) synthesis using metal nanoparticles as a catalyst. This substrate connects Cu interconnect layers on its both surfaces. The companies have already succeeded in lowering via resistance to W plug level by forming highly dense metal nanoparticles, which result in concentrated CNTs. They also developed a process technology to planarize the substrate surfaces by coating grown CNTs with a SOG (spin on glass) material. Fujitsu insisted this technology has boosted the compliance with Si manufacturing process. This is the first time the companies companies unveiled the planarized wafer for the first time.