Renesas Develops High-density Capacitorless Memory Aimed at Replacing Embedded DRAMs for 65-nm Generation and Beyond

Sept 28, 2005 14:42

Renesas Technology Corp. has developed a high-density memory "TTRAM (twin transistor RAM)" to be embedded in system-on-a-chip (SoC) devices built with 65-nm and later generation processes. The new memory is targeted for replacing the existing embedded DRAMs for SoC. The TTRAM memory cell includes two MOS transistors formed on a silicon-on-insulator (SOI) substrate. This configuration eliminates the need for a capacitor that is necessary in the existing DRAMs, thereby realizing higher density memory devices for 65-nm and subsequent generation processes.

Renesas has prototyped a 2-Mbit test chip using 130-nm generation SOI CMOS technology. In continuous data output mode, the operating frequency achieved by the test chip is 250 MHz, which is roughly equivalent to that by an embedded DRAM. In random access mode, the operating frequency is as fast as 133 MHz. The power consumption when operating at 250 MHz in continuous data output mode is 148 mW, which is about 43% less than the power consumed by a Renesas previous embedded DRAM built with the same generation CMOS technology. The chip requires 100 ms to retain data at room temperature. The memory cell of the chip measures 0.33 μm², while the area of the same generation embedded DRAM is 0.35 μm².

TTRAM uses two transistors connected in series on the SOI substrate as the memory cell. One is used as a storage transistor which corresponds to the existing DRAM capacitor, while the other is an access transistor. Data reads and writes are performed by controlling a conduction state of the access transistor and a floating-body potential of the storage transistor. When writing "0" data, the floating-body potential is set to low and the access transistor is turned "on," while writing "1" data, the former is set to high and the latter is turned "off." Data reads are performed by using a difference in turn-on current of the access transistor appearing according to the floating-body potential state. Since these memory cell operations do not require a step-up or negative voltage as DRAM cells do, TTRAM is suitable for applications in miniaturization processes and lower voltage operations.

Motoyuki Ooishi, Nikkei Electronics

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