Continued from New ¡ÈSandy Bridge¡É Architecture to be Rolled Out by End 2010
At IDF Beijing, Intel showed the Single-chip Cloud Computer (SSC) message-passing microprocessor, which integrated 48 Pentium-equivalent CPU cores. The SCC provides each CPU core with 256Kbytes of secondary cache, but hardware is not provided with a mechanism to ensure cache integrity. This decision was made to minimize chip size.
Instead, the company is researching a method of ensuring cache integrity via software, using virtual memory space shared by all cores. A demonstration of Black-Scholes computation, often used in the financial sector, showed that processing speed was about 28 times faster running in 32 cores than in a single core, demonstrating that the software cache control scheme imposes few performance penalties.
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