Sony LSI Design Inc of Japan has implemented a Double-Data-Rate3 (DDR3) synchronous dynamic random access memory (SDRAM) signal transfer subsystem on an inexpensive printed circuit board (PCB). The integrated chip-package-board simulation needed to design and evaluate the subsystem was presented at the Synopsys User Meeting 2009 in Shinagawa, Tokyo, on October 14.
The presenter - Toru Takaira, assistant
manager, Sec 5, Analog Technology Dept, LSI Design Div 2, Sony LSI
Design - explained that DDR3 SDRAM chips are being extensively used in
PCs now. If prices remain stable, he said, the next stage will be their
adoption in digital consumer electronics developed by Sony Corp and
other firms. Takaira's group is preparing for this next stage now.
Cost is a critical factor in digital consumer electronics, and if possible, boards, packages and other components have to be made inexpensively. The 1066Mbps DDR3 subsystem presented was implemented as a wire-bonded package, not a flip-chip, and instead of using a build-up board, engineers used a regular board with through-hole vias. One design goal was to limit the number of layers to four.
There was some question as to whether a wire-bonded package could attain a signal throughput of 1055Mbps mounted on a 4-layer board with through-hole vias, so Sony LSI Design used chip-package-board co-simulation to develop and evaluate the design. The simulation treated the signal path between the DDR SDRAM working memory and the high-performance system-on-chip (SoC), such as that which is used for image processing and similar operations. If no problems showed up in the simulation verification or prototype board measurements, the subsystem design results could be copied to the actual product for use.
The simulated signal path was composed of multiple models: the SoC model, the SoC package model, the board-pattern model and the SDRAM (including its package) model. The SoC model was the Simulation Program with Integrated Circuit Emphasis (SPICE) model from Synopsys Inc of the US, and the memory model was received from a memory manufacturer as a packaged Input/output Buffer Information Specification (IBIS) model. The SoC package and board wiring models were created with an electromagnetic field simulator. The package was an RLC model, while the PCB model used the "S" parameter.
The simulator was the HSPICE circuit simulator from Synopsys because, as Takaira explained, "The HSPICE model encryption method is industry-standard, making it easy to obtain models from semiconductor and other manufacturers." HSPICE simulation was used to monitor simultaneous switching results for all data signals (32 bits), and simulation results were compared to measurement results from the prototype board.
Takaira explained that the HSPICE execution results closely matched actual measurements for many node signals, and large eye patterns were found in both simulation and measurement, indicating that the design was a success. The development team ran multiple simulations and even made new board prototypes to optimize the design before attaining these results.
Takaira explained that the initial target of 1066Mbps was easily cleared in both simulation and actual measurement, and in fact the designed subsystem experienced no problems even at 1140Mbps (equivalent to 570MHz).
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