Toyota Technical Development Corp (TTDC), a wholly owned subsidiary of Toyota Motor Corp of Japan, made a presentation about a high-efficiency design method for automotive analog integrated circuits (IC), at the Electronic Design Automation (EDA) Tech Forum 2009 Tokyo, Sept 4, in Shinagawa, Tokyo. The presenter - Jun Kobayashi, Electronics Development Div 3, TTDC - revealed that advances in analog circuit reuse make it possible to reduce design man-hours by half.
About a year earlier, Kobayashi announced at a private event held by Jedat Inc of Japan that he was working with Jedat on improving the efficiency of analog IC layout design, and that they had cut the number of man-hours required for design by 75% - 84%. He explained then that the efficiency improvement came from better layout design reuse, with the reuse ratio pushed up to at least 70%.
Circuit design efficiency was improved this time through a cooperative effort with Mentor Graphics Corp of the US and Mentor Graphics Japan Co Ltd, instead of with Jedat. The key priority was promoting circuit reuse, which in this case means using intellectual property (IP) cores. Kobayashi predicted that the analog ICs used for automotive control applications will grow significantly in circuit scale, and added that his development project was launched in the expectation that more efficient design methods would be needed.
The first step of the project was to survey the state of circuit reuse in the industry, which he discovered was much lower than he had expected. While reuse levels vary with circuit type, generally the reuse ratio was between 4% and 40%.
The reason, he said, was that while circuits with specific applications such as bandgap reference voltage sources and 5V regulators have been implemented as IP cores, circuits with varying circuit parameters, like opamps and comparators, have not.
Unless the circuits have been turned into IP cores, every time they are used, even in the identical circuit topology, the circuit schematics and test bench have to be input manually. Kobayashi's group worked on converting such circuits to IP cores. They locked in the circuit topology and test bench, retaining application flexibility by supporting parameters for circuit specification and simulation.
TTDC formulated two strategies to improve utilization efficiency for these IP cores. The first is automating the target value determination for circuit optimization. Values input as design specifications are used as targets for circuit optimization.
The second strategy is improving circuit simulation by taking variation into account. The conventional process is a cycle consisting of parameter set/revise - simulation - waveform check, which means that while half-long simulations are in progress, design engineers can only twiddle their thumbs.
In the new approach, all parameters are set in advance and a batch simulation run. Waveforms are checked after all simulations are complete. The waiting times occur in a single block, making it easier for designers to spend their time effectively on other tasks.
Circuit simulator set-up, control, etc, are of course necessary when executing the circuit optimization, circuit simulation incorporating variation and similar actions. TTDC selected Mentor Graphics' ICAnalyst to handle these tasks. In the last part of his presentation, Kobayashi mainly discussed effective utilization of ICAnalyst, for example, he introduced a method of setting up recommended optimization parameters in accordance with target specifications.
Future plans include tie-ups in layout design and circuit optimization, utilization of analog description language, and quantization of the effectiveness of the design methods introduced. Kobayashi estimates his approach will "probably cut total circuit design man-hours by about half".
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