Nikkei Electronics Asia -- October 2009
Design View from Japan
TSMC, EDA Users Make Big Splash at DAC 2009

The biggest event in the electronic design automation (EDA) industry, Design Automation Conference (DAC), was held in San Francisco, California in July this year. DAC 2009 may have been the 46th time the event was held, but never before has it been held in such difficult circumstances. This is because the semiconductor manufacturers - the major EDA customers - are in a slump. The semiconductor market is said to have finally bottomed out, but even so, the scale of the market overall has shrunk roughly to what it was about five years ago, back in 2004.

The official announcement by DAC 2009 organizers put this year's attendance at 7,996 (5,299 visitors plus 2,697 exhibition staffers), only just beating last year's total of 7,770 for DAC 2008, held in unpopular Anaheim, California.

TSMC's RDF Rev 10.0

Taiwan Semiconductor Manufacturing Co Ltd (TSMC) made a bigger splash than ever at the exhibition. The company had a huge booth, including sub-booths for at least ten partner firms participating in the TSMC Open Innovation Forum.

TSMC announced Rev 10.0 of its Reference Design Flow, the implementation design procedure it is championing, to handle manufacturing technology for 28nm-generation chips.

Reference Design Flow 10.0 covers not only chip design, but has also been expanded for the first time to include package design (system-in-package, or SiP) as well. The change was made because with higher chip speeds and other advances, less than optimal package design can prevent the chip from attaining design performance, or lead to various post-shipment problems. Shauh-Teh Juang, senior director, Design Infrastructure Marketing Division Design & Technology Platform, explained that the reference design flow will be expanded in the future to cover chip-package-board co-designs.

The TSMC Reference Design Flow incorporates a number of EDA tools, primarily for automatic layout design. It previously offered only three flows, for Cadence Design Systems, Synopsys Inc and Magma Design Automation Inc, all of the US. In 10.0, however, a fourth flow has appeared, based on the tools from Mentor Graphics Corp of the US.

User Track

At this year's DAC, there were many conference sessions from EDA users, which included a User Track for the first time.

DAC was originally founded as a place for EDA developers to announce their latest technology, but the increased complexity of system-on-chip (SoC) products manufactured using state-of-the-art manufacturing technology has made it impossible to boost design efficiency merely by introducing a new technology into one specific design step. It has become crucial to use multiple tools together, and to use them effectively. The user presentations helped explain how they are being used.

There were a large number of applications to present in the User Track, resulting in nine paper sessions and a poster session. One poster session presenter suggested that people who didn't get nominated for a paper ended up in a poster session. But the poster sessions were, in fact, more active than the papers, as the presenters were available and easy to talk to. In addition to the User Track, there was an unusually high ratio of papers on how to utilize technologies, tools, etc, in the regular sessions as well.

Professor Andrew B Kahng of the University of California, who served as the general chair for the 46th DAC, said that user-oriented presentations, such as those that were featured in the User Track, would feature again in the 47th DAC (DAC 2010), June 13-18, at Anaheim, California.

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