Nikkei Electronics Asia -- September 2009
Design View from Japan
Fujitsu: TLM Co-Simulation Slashes SoC Design Cost

Sept 18, 2009 00:00 Ikutaro Kojima

Fujitsu Microelectronics Ltd (FML) of Japan has disclosed the results of applying SystemC transaction level modeling (TLM) 2.0 in integrated circuit (IC) hardware-software co-simulation. The presentation was made on July 10 at SystemC Japan 2009, organized by CoWare Japan KK, Mentor Graphics Japan Co Ltd and Forte Design Systems Japan.

Many companies in Japan are interested in SystemC as an input language for behavioral synthesis tools, but on the international scene it is generally thought more important as a means to improving simulation efficiency. In particular, it is important for improving the practical utility of co-simulation using TLM hardware modeling, which delivers a higher level of abstraction than the register transfer level (RTL). The Open SystemC Initiative (OSCI), a SystemC promotion group, completed the TLM 2.0 standard in June 2008.

Major Cost Savings

FML announced Cedar-ESL in May 2007 (when the company was still a division of Fujitsu Ltd of Japan), providing application-specific IC (ASIC) and other customers with an embedded software verification environment based on TLM co-simulation. According to Kazumasa Nakamura project manager, Front-end Design & Verification Dept, SoC Design Engineering Div, Common IP Technology Development Unit at FML, who made the presentation, TLM co-simulation technology has been applied in numerous chip designs both in-house and at other firms (via Cedar-ESL) since the announcement in May 2007.

Nakamura discussed various applications, but mostly talked about the ML86298 graphic display controller IC for vehicular use, released by the firm in March 2009.

When the group performed co-simulation based on a TLM 2.0 hardware model, they discovered that it provided not only improvements in software quality, development time and other points, but also major cost savings. "We reduced costs by about Yen200 million," said Nakamura. This amount includes manufacturing costs such as mask rework, but as Nakamura explains, "Reduction in the verification cost of hardware and software accounted for the majority of the cost reduction."

The cost reductions this time were due to an early discovery that the OpenGL standard had been misinterpreted by both the IC circuit block hardware designer and the host central processing unit (CPU) middleware designer. As a result, the hardware block specification drawn up by the hardware designer had been faulty. Nakamura explained: "In the conventional development approach, without TLM co-simulation, we wouldn't have noticed this error until we put the prototype chip on a test board, and that would have been six months later."

Adjustment for Designers

RTL hardware design was carried out in parallel with software design, as was the development of a SystemC TLM model for co-simulation. Any changes to the hardware design, SystemC model, etc, also therefore affected software design.

Nakamura admitted that many designers had trouble accepting the idea that underlying portions (device drivers, hardware, etc, for the middleware designers, or middleware for the application software designers, for example) of the design could change.

The sample application software ( to verify the characteristic specifications of the MB86298) was completed before the chip sample, which would have been impossible with the past development style. The sample application software was completed a full six months before it could have been ready with the standard methodology. 

While discussing the MB86298 co-simulation project, Nakamura also revealed the group used the OSCI reference simulator to run the SystemC model, which is free; the group did not use any products from electronics design automation (EDA) vendors.

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