Copper wiring, strained silicon, silicon-on-insulator (SOI) - IBM has pioneered a host of new semiconductor technologies adopted later by other firms. We spoke with Bernard Meyerson, IBM Fellow and chief technical officer (CTO) of the Systems & Technology Group - which includes microelectronics - about semiconductor manufacturing in the future.
People have been saying for years that we have reached the limit of
Moore's Law. Where do you think the limit is? Do you think the pace is
slacking?Rule reduction in complementary metal-oxide semiconductor (CMOS) technology stopped two or three generations ago, for traditional methods. There was a recipe for CMOS scaling, which was to shrink the dimensions of the transistor by a given percentage every generation.
As the generations advanced, eventually we reached the point where a given area held twice as many transistors, and transistor dissipation was halved. That worked because total transistor dissipation remained the same for the chip as a whole, even with twice as many transistors.
Gate oxide films and other layers that had to be reduced in size just became too thin, so that even if the dimensions shrank in accordance with Moore's Law, dissipation remained constant. For a chip of a given area, a new generation began to show an increase in dissipation. Some manufacturers who failed to notice that manufactured chips with unacceptably high dissipation, and were forced to cancel production and start over again from the initial development stage. That was maybe five, six years ago.
In 2001, IBM Corp of the US resolved the problem. We used multiple cores to achieve excellent processing performance without having to jack the frequency up so high. It took other manufacturers four or five years to follow suit.
There's an even bigger opportunity right now. I think Moore's Law will continue to apply, but it'll be a little different.
All Moore's Law says is that the number of transistors in a given area will double every 12 to 18 months.
Many people seem to think that means transistors have to be made smaller, but that's wrong. There are other ways. The resolution in chip fabrication will continue to shrink for some time to come, probably down to 22nm or 15nm. It will eventually slow down, though, or perhaps stop entirely.
Moore's Law won't stop, however, only dimensional shrink. Other methods will be used to boost circuit density, such as three-dimensional (3D) stacking. Chips can be fabricated with any number of transistors stacked on top of each other.
Two chips can be stacked to double the number of transistors in the footprint of one. And this also follows Moore's Law just fine.
Yes, I do. We are already implementing 3D technology in telecommunication integrated circuits (IC). Our Burlington fab, in Vermont, the US, is already stacking chips and interconnecting them, because we need stacked chips to provide a particular telecommunication function. In the future it will be possible to make 3D microprocessors.
When we manufacture telecommunication ICs now, we use through silicon vias (TSV) to stack chips. An actual hole is opened up in the silicon to connect the adjacent chips. We use this approach, for example, in power amplifiers for mobile phones and other products. This simple example can be extended to microprocessors and other more complicated layouts.
IBM already has the capability, and we are already making the transition to 3D. It will take several years to complete, though. Multicore chips hit the market in 2001, but it wasn't until about 2005 that most manufacturers were shipping multicore product. It will probably take three or four years for 3D to take hold, too. The first step will probably be multichip processors, stacked together with memory chips. Instead of mounting ICs on opposite sides of the board and passing data between them, data handling is a lot more efficient when you're dealing with two chips stacked together.
These days about half of the dissipation in microprocessors comes from communication with external memory chips. If these chips are stacked together in 3D, communication energy cost might drop to a tenth. That's a considerable improvement. We are already learning a lot about how to accomplish this.
What types of IC is 3D architecture appropriate for?It's not the right choice for everything. It works best in situations where there is a single microprocessor with multiple memory chips on top, for example, but wouldn't be very useful when several power-hungry microprocessors are stacked together. The chip in the middle wouldn't be able to radiate enough heat.
From the aspect of radiating heat, it might make sense to sandwich a low-dissipation memory chip between two microprocessors. You'd only have to cool the microprocessors on the outside. The chip on the inside is memory, which generates very little heat. You'd have to be careful about which chips to use, and how to position them, though.
Industry will always be working toward smaller rules, because they mean lower cost. Rule shrink will continue whether 3D technology is used in current products or not, but I think the pace will slacken off. And if design features get small enough, eventually conventional silicon chips become impossible. For 15nm-generation technology, for example, it may be necessary to switch from today's planar transistors to transistors with a completely new architecture.
Metallization is also becoming a major problem. Transistors have been shrinking, moving to smaller geometries, for 40 years now, steadily improving performance. The transfer rate through wiring, though, has gotten significantly slower.
Even if transistors were infinitely fast, chip speeds would still be restrained by the metallization.
IBM was the first to come up with an innovation here, too: a totally different approach we call Airgap technology. With Airgap, there are no dielectrics between wiring layers. There isn't anything between them, in fact. It isn't just a lab experiment anymore. IBM has a standing policy of only announcing technologies already confirmed as fully operational. Chips using Airgap technology have been prototyped, and a giant Airgap microprocessor functions perfectly. Airgap makes it possible to use the same transistors as always, but significantly boosts chip operating speed.
Research is well under way into extreme ultraviolet (EUV) steppers, for the next generation, and one after that. These systems can handle extremely small line widths, and are really incredible. The question is when they will become available. They are enormous, complex pieces of equipment. We don't think they'll be ready in time for 22nm-generation production. This is a major problem for the whole industry.
interviewed by Motoyuki Oishi
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